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參數(shù)資料
| 型號： | 2K30A |
| 廠商： | Motorola, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 219K |
| 代理商： | 2K30A |
Chip Errata
DSP56301 Digital Signal Processor
Mask:2K30A
DSP56301 Errata
1996-2002, Motorola
For More Information On This Product,
Go to: www.freescale.com
ng 12/19/02 pg. 5
ED13
Description (added 5/ 15/ 98):
When the HI32 is in PCI mode, the Insert Address Enable control
bit (IAE=1) can be set only with the Receive Buffer Lock Enable
control bit set (RBLE=1 in the DPCR register.)
Description (added 7/ 21/ 98):
2K30A
ED15
The DRAM Control Register (DCR) should not be changed while
refresh is enabled. If refresh is enabled only a write operation that
disables refresh is allowed.
Workaround:
First disable refresh by clearing the BREN bit, than change other
bits in the DCR register, and finally enable refresh by setting the
BREN bit.
Description (added 9/ 28/ 98):
2K30A
ED17
In all DSP563xx technical datasheets, a note is to be added under
"AC Electrical Characteristics" that although the minimum value
for "Frequency of Extal" is 0MHz, the device AC test conditions are
15MHz and rated speed.
Workaround:
N/ A
Description (added 11/ 2/ 98):
2K30A
ED18
The PCI host must not change the values of the HBE[3:0] bits
during PCI read transactions from the HI32 as a PCI target.
Description (added 11/ 9/ 98):
2K30A
ED19
To guarantee the proper HI32 operation, the DMA should service
the HI32 under the following restrictions:
Two DMA channels should not service the DRXR FIFO if
master and slave data is mixed there.
The DMA data transfers should not be concurrent with the
56300 Core data transfers to/from the same HI32 data
FIFO.
2K30A
Errata
Number
Document Update
Applies
to Mask
F
Freescale Semiconductor, Inc.
n
.
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