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參數(shù)資料
| 型號： | 2SC5677-FB-A |
| 元件分類： | 小信號晶體管 |
| 英文描述： | L BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
| 封裝： | LEADLESS MINIMOLD PACKAGE-3 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 97K |
| 代理商： | 2SC5677-FB-A |
LC07410LG
No.A1345-14/36
3V Regulator
Built-in 3V Regulator for VDDA,VDDP.
The regulator starts by setting as REG_PDX = 1.
Output current is 100mA (typ).
It provides with max 200mA (typ) output current limiter for over-current protective function.
Microphone (MIC) amplifier
The microphone amplifier has a differential input and a gain of +26dB (typ).
Its gain can also be set to +20dB or 0dB by register MGAIN [1:0]. Its input resistance is 70k
Ω (typ). The MICPWR is a
power output pin for the microphone, and its output voltage is 2.3V (typ 0.767
×VDDA).
The maximum output current is 20mA.
The microphone amplifier is placed in the power down mode by setting MIC_PDX to 0.
When MIC_PWR_PDX is set to 0, the microphone power supply circuit is placed in the power down mode.
ADRS
Bit
Name
Init
Description
02h
[5:4]
MIC_GAIN
01b
MIC amplifier circuit, gain setting
11: 26dB 10: 20dB 01: 0dB 00: 0dB
Recording system automatic level control (ALC)
The amplifier gain of the PGA (Programmable Gain Amplifier) must be automatically adjusted so that the A/D
converter output audio level is setup to the predetermined value. The gain can be varied within a range (maximum) of
-14dB to +34dB.
When using ALC in the recording system, set REC_ALC to 1 and PB_ALC to 0 (recording system ALC mode).
When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the PGA is placed in the manual mode, and the
amplifier gain is fixed to the value of the ALC_GAIN register setting.
When PGA_PDX is set to 0, the PGA is placed in the power down mode. During normal use, the state of PGA_PDX
must be switched at the same time as ADC_PDX.
For further details on operation, refer to “Description of ALC/limiter (Automatic Level Control) operation.”
Any of eight recording ALC levels (in 1dB steps from -3dBFS to -10dBFS) can be set using the ALC_VAL register.
ADRS
Bit
Name
Init
Description
[6:4]
ALC_VAL
001b
Set the ALC limiter level
000: -3dBFS 001: -4dBFS 010: -5dBFS 011: -6dBFS
100: -7dBFS 101: -8dBFS 110: -9dBFS 111: -10dBFS
03h
[2:0]
ALC_FA1
010b
Attack coefficient 1 setting
[6:4]
ALC_THA
010b
Set the attack speed switch over thresh
04h
[2:0]
ALC_FA2
100b
Attack coefficient 2 setting
[6:4]
ALC_THR1
011b
Set the recovery speed switch over thresh1
05h
[2:0]
ALC_FR1
100b
Recovery coefficient 1 setting
[6:4]
ALC_THR2
011b
Set the recovery speed switch over thresh2
06h
[2:0]
ALC_FR2
100b
Recovery coefficient 2 setting
07h
[2:0]
ALC_FR3
100b
Recovery coefficient 3 setting
[7]
ALC_FULLEN
0b
Sets the full scale detection mode
1: Performs attack operation regardless of the ALCZCD setting when a full scale is detected.
0: Normal operation
[6]
ALC_ZCD
1b
Controls the gain change operation at zerocross timing.
1: Changes the gain at zerocross timing.
0: Changes the gain without waiting for a zerocross timing.
[5:4]
ALC_ZCDTM
01b
Set the zerocross detection timeout time. Valid when [ALC_ZCD] = 1.
11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs
* It becomes the above-mentioned 1/4 times at fs 8k to12kHz,
It becomes the above-mentioned 1/2 times at fs 16k to 24kHz.
[3:2]
ALC_TLIM
01b
Set the inter-zerocross attack limit.
11: 4dB 10: 2dB 01: 1dB 00: 0.5dB
Valid when [ALC_ZCD] = 1
08h
[1:0]
ALC_RWT
10b
Set the recovery alert time
11: 1024/fs 10: 512/fs 01: 256/fs 00: 128/fs
* It becomes the above-mentioned 1/4 times at fs 8k to 12kHz,
It becomes the above-mentioned 1/2 times at fs 16k to 24kHz.
Continued on next page.
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