參數(shù)資料
型號(hào)： 2SC5677-FB
元件分類(lèi)： 小信號(hào)晶體管
英文描述： L BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR
封裝： LEADLESS MINIMOLD PACKAGE-3
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 97K
代理商： 2SC5677-FB
LC07410LG
No.A1345-19/36
Noise gate function
The noise gate function is enabled when NGEN is 1. This function cannot be used during PB-ALC mode.
If the PGA input level continues at or below NGTH[2:0] for the period NGDT[1:0], the volume after ADC output is
decreased from 0dB to approximately -35dB at the rate NGDT[1:0].
If the PGA input level rises to NGTH+6dB or more, the volume after ADC output is increased from approximately
-35dB to 0dB at the rate NGRT[1:0].
Input
Output
VOL gain
Silent detection thresh
Noise gate: Valid
Noise gate: Invalid
Silent detection thresh
Return level of detection thresh
Silent detection time
Amplitude detection phase
ADC
PGA output undergoes AD conversion and is output as 16-bit serial audio data. The three formats, I2S, left justified, and
right justified are supported.
If ADC_PDX is set to 0, the ADC block is powered down. An interval of 64/fs is used as the ADC initialization interval
(initialization + data delay) from the point power down is canceled. When power is turned on, initialization is required
when switching the system clock.
A digital HPF for canceling DC offset is built-in. The cut-off frequency, fc, is 1.85Hz (@fs = 48kHz).
The full-scale voltage (0dBFS) is 0.6
×VDDA.
DAC
16-bit serial audio data undergoes DA conversion. The three formats, I2S, left justified, and right justified are supported.
If DAC_PDX is set to 0, the DAC block is powered down. An interval of 58/fs is used as the DAC initialization interval
(initialization + data delay) from the point power down is canceled. When power is turned on, initialization is required
when switching the system clock.
The full-scale voltage (0dBFS) is 0.6
×VDDA.
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