參數(shù)資料
型號: 2SK3585G
廠商: PANASONIC CORP
元件分類: 小信號晶體管
英文描述: 0.46 mA, N-CHANNEL, Si, SMALL SIGNAL, JFET
封裝: ROHS COMPLIANT, SSSMINI3-F2, 3 PIN
文件頁數(shù): 1/3頁
文件大?。?/td> 264K
代理商: 2SK3585G
Silicon Junction FETs (Small Signal)
Publication date: October 2008
SJF00109AED
1
This product complies with the RoHS Directive (EU 2002/95/EC).
2SK3585G
Silicon N-channel junction FET
For impedance conversion in low frequency
For electret capacitor microphone
Features
High mutual conductance gm
Low noise voltage NV
Absolute Maximum Ratings Ta = 25°C
Parameter
Symbol
Rating
Unit
Drain-source voltage (Gate open)
VDSO
20
V
Drain-gate voltage (Souece open)
VDGO
20
V
Drain-source current (Gate open)
IDSO
2
mA
Drain-gate current (Souece open)
IDGO
2
mA
Gate-source cut-off current (Drain open)
IGSO
2
mA
Power dissipation
PD
100
mW
Operating ambient temperature
Topr
–20 to +80
°
C
Storage temperature
Tstg
–55 to +125
°
C
Electrical Characteristics Ta = 25°C±3°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Drain current *1
ID
VDS = 2.0 V, Rd = 2.2 kW ± 1%
100
460
m
A
Drain-source current
IDSS
VDS = 2.0 V, Rd = 2.2 kW ± 1%, VGS = 0
107
470
m
A
Mutual conductance
gm
VD = 2.0 V, VGS = 0, f = 1 kHz
660
1600
m
S
Noise voltage
NV
VD = 2.0 V, Rd = 2.2 kW ± 1%
CO = 5 pF, A-curve
4
m
V
Voltage gain
GV1
VD = 2.0 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV, f = 1 kHz
–7.5
–4.7
dB
GV2
VD = 12 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV, f = 1 kHz
–4.0
–1.5
GV3
VD = 1.5 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV, f = 1 kHz
–8.0
–5.0
D
GV . f *2
VD = 2.0 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV
f = 1 kHz to 70 Hz
0
1.7
Voltage gain difference
GV2 – GV1
0
4.0
dB
GV1 – GV3
0
1.7
Gate resistance
Rg
VGS = 0.05 V
8
15
GW
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.
2. A protection diode is built-in between gate and source of transistor. However if forward current ows between gate and source transistor
might be damaged. So please be careful not insert reverse.
3. *1: ID is assured for IDSS .
*2: D|GV . f | is assured for AQL 0.065. (The measurement method is used by source-grounded circuit.)
Package
Code
SSSMini3-F2
Pin Name
1: Drain
2: Source
3: Gate
Marking Symbol: 5K
Ma
int
en
an
ce
/
Dis
co
nti
nu
ed
Maintenance/Discontinued
includes
following
four
Product
lifecy
cle
stage.
planed
maintenance
type
maintenance
type
planed
discontinued
typed
discontinued
type
Please
visit
following
URL
about
latest
information.
http://panasonic.net/sc/en
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