參數(shù)資料
型號: 33742S
廠商: Motorola, Inc.
元件分類: CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片的增強型(SBC)的高速CAN收發(fā)器
文件頁數(shù): 13/52頁
文件大小: 1087K
代理商: 33742S
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33742
13
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V
V2
5.25 V, 5.5 V
V
SUP
18 V, and -40
°
C
T
A
125
°
C. Typical values noted
reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING
(Note 28)
SPI Operation Frequency
f
REQ
0.25
4.0
MHz
SCLK Clock Period
t
PCLK
250
N/A
ns
SCLK Clock High Time
t
WSCLKH
125
N/A
ns
SCLK Clock Low Time
t
WSCLKL
125
N/A
ns
Falling Edge of
CS
to Rising Edge of SCLK
t
LEAD
100
N/A
ns
Falling Edge of SCLK to Rising Edge of
CS
t
LAG
100
N/A
ns
MOSI to Falling Edge of SCLK
t
SISU
40
N/A
ns
Falling Edge of SCLK to MOSI
t
SIH
40
N/A
ns
MISO Rise Time
(Note 29)
C
L
= 220 pF
t
RSO
25
50
ns
MISO Fall Time
(Note 29)
C
L
= 220 pF
t
FSO
25
50
ns
Time from Falling or Rising Edges of
CS
MISO Low Impedance
MISO High Impedance
t
SOEN
t
SODIS
50
50
ns
Time from Rising Edge of SCLK to MISO Data Valid
0.2 V
DD
MISO
0.8 V
DD
, C
L
= 200 pF
t
VALID
50
ns
STATE MACHINE TIMING
Delay Between
CS
LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation
(Note 30)
t
CS
-STOP
18
34
μ
s
Interrupt Low-Level Duration
Stop Mode
t
INT
7.0
10
13
μ
s
Internal Oscillator Frequency
(Note 31)
f
OSC
100
kHz
Watchdog Period Normal and Standby Modes
Period 1
Period 2
Period 3
Period 4
t
WD
8.58
39.6
88
308
9.75
45
100
350
10.92
50.4
112
392
ms
Notes
28.
29.
30.
31.
See
Figure 4, SPI Timing Diagram
, page 17.
Not production tested. Guaranteed by design.
Not production tested. Guaranteed by design. Detected by V2 OFF.
f
OSC
is indirectly measured (1.0 ms reset) and trimmed.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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