MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Semiconductor Components Industries, LLC, 2001
August, 2001 – Rev. 13AB
1
Case Outline Number:
369A
CASE 369A–13
ISSUE AB
DATE 07/27/2001
DPAK
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
D
A
K
B
R
V
S
F
L
G
2 PL
M
0.13 (0.005)
T
E
C
U
J
H
–T–
SEATING
PLANE
Z
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
MIN
0.235
0.250
0.086
0.027
0.033
0.037
0.180 BSC
0.034
0.018
0.102
0.090 BSC
0.175
0.020
0.020
0.030
0.138
MAX
0.250
0.265
0.094
0.035
0.040
0.047
MIN
5.97
6.35
2.19
0.69
0.84
0.94
4.58 BSC
0.87
0.46
2.60
2.29 BSC
4.45
0.51
0.51
0.77
3.51
MAX
6.35
6.73
2.38
0.88
1.01
1.19
MILLIMETERS
INCHES
0.040
0.023
0.114
1.01
0.58
2.89
0.215
0.050
---
0.050
---
5.46
1.27
---
1.27
---
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
1
2
3
4
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
MARKING
DIAGRAMS
xxxxxxxxx = Device Code
A
= Assembly Location
lL
= Wafer Lot
Y
= Year
WW
= Work Week
YWW
xxxxxxxx
xxxxx
ALYWW
x
Discrete
Integrated
Circuits
ON Semiconductor
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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