3D3428
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D3428 – LOW NOISE)
FEATURES
All-silicon, low-power CMOS technology
3.3V CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Leading- and trailing-edge accuracy
Programmable via serial or parallel interface
Increment range:
0.25 through 15.0ns
Delay tolerance:
0.5% (See Table 1)
Supply current:
2mA typical
Temperature stability:
±
1.5% max (-40C to 85C)
Vdd stability:
±
1.0% max (3.0V to 3.6V)
FUNCTIONAL DESCRIPTION
The 3D3428 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:
T
i,nom
= T
inh
+ i * T
inc
where i is the programmed address, T
inc
is the delay increment (equal
to the device dash number), and T
inh
is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.
The all-CMOS 3D3428 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount
16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
DELAYS AND TOLERANCES
NUMBER
Inherent
Delay (ns)
Range (ns)
Step (ns)
Frequency
3D3428-0.25
11.5
±
2.0
63.75
±
0.4
0.25
±
0.15
6.25 MHz
3D3428-0.5
11.5
±
2.0
127.5
±
0.8
0.50
±
0.25
3.12 MHz
3D3428-1
11.5
±
2.0
255.0
±
1.5
1.00
±
0.50
1.56 MHz
3D3428-1.5
11.5
±
2.0
382.5
±
2.3
1.50
±
0.75
1.04 MHz
3D3428-2
11.5
±
2.0
510.0
±
2.0
2.00
±
1.00
781 KHz
3D3428-2.5
13.0
±
2.5
637.5
±
2.5
2.50
±
1.25
625 KHz
3D3428-4
15.5
±
4.0
1020
±
4.0
4.00
±
2.00
390 KHz
3D3428-5
18.0
±
5.0
1275
±
4.0
5.00
±
2.50
312 KHz
3D3428-7.5
23.0
±
7.5
1912.5
±
6.0
7.50
±
3.75
208 KHz
3D3428-10
27.5
±
10
2550
±
8.0
10.0
±
5.00
156 KHz
3D3428-15
38.0
±
15
3825
±
12
15.0
±
7.50
104 KHz
NOTES: Any delay increment between 0.25 and 15 ns not shown is also available as standard.
See application notes section for more details
data
delay
devices,
inc.
3
PACKAGES
1
2
3
4
8
7
6
5
IN
SO
AE
GND
VDD
OUT
SC
SI
3D3428Z-xx SOIC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN
AE
SO/P0
P1
P2
P3
P4
GND
VDD
OUT
MD
P7
P6
SC
P5
SI
3D3428-xx DIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
AE
SO/P0
P1
P2
P3
P4
GND
VDD
OUT
MD
P7
P6
SC
P5
SI
3D3428S-xx SOL
here.