參數資料
型號: 3D7205G-100
廠商: Electronic Theatre Controls, Inc.
英文描述: MONOLITHIC 5-TAP FIXED DELAY LINE
中文描述: 整體式5 - TAP在固定延遲線
文件頁數: 3/4頁
文件大小: 256K
代理商: 3D7205G-100
Doc #96007
12/2/96
3D7205
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
APPLICATION NOTES (CONT’D)
custom reference designator
identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7205 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The
thermal coefficient
is reduced to
600
PPM/C
, which is equivalent to a variation , over
the 0C-70C operating range, of
±
3%
from the
room-temperature delay settings. The
power
supply coefficient
is reduced, over the 4.75V-
5.25V operating range, to
±
2%
of the delay
settings at the nominal 5.0VDC power supply.
It
is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
DC Supply Voltage
V
DD
Input Pin Voltage
V
IN
Input Pin Current
I
IN
Storage Temperature
T
STRG
Lead Temperature
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
Static Supply Current*
I
DD
High Level Input Voltage
V
IH
Low Level Input Voltage
V
IL
High Level Input Current
I
IH
Low Level Input Current
I
IL
High Level Output Current
I
OH
MIN
2.0
-250
MAX
15
0.8
1
-4.0
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
Low Level Output Current
I
OL
4.0
mA
Output Rise & Fall Time
T
R
& T
F
2
ns
*I
(Dynamic) = 5 * C
* V
* F
where: C
LD
= Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
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