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參數(shù)資料
| 型號(hào)： | 3D7205H-100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 中文描述： | 整體式5 - TAP在固定延遲線 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 256K |
| 代理商： | 3D7205H-100 |
3D7205
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7205 five-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a
Maximum
and
an
Absolute Maximum
operating input
frequency and a
Minimum
and an
Absolute
Minimum
operating pulse width have been
specified.
OPERATING FREQUENCY
The
Absolute Maximum Operating Frequency
specification, tabulated in
Table 1
, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The
Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
To guarantee the
Table 1
delay accuracy for
input frequencies higher than the
Maximum
Operating
Frequency
, the 3D7205 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification,
the part number will include a
custom reference designator
identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
OPERATING PULSE WIDTH
The
Absolute Minimum Operating Pulse
Width
(high or low) specification, tabulated in
Table 1
, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The
Minimum Operating Pulse Width
(high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in
Table 1
is
guaranteed.
To guarantee the
Table 1
delay accuracy for
input pulse width smaller than the
Minimum
Operating Pulse
Width
, the 3D7205 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the
part number will include a
VDD
O1
IN
O2
O3
O4
Temp & VDD
Compensation
GND
Figure 1: 3D7205 Functional Diagram
20%
20%
20%
20%
20%
O5
Doc #96007
12/2/96
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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| 3D7205H-20 | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205H-25 | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205H-30 | MONOLITHIC 5-TAP FIXED DELAY LINE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7205H15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7205H-15 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205H20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7205H-20 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205H25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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