參數(shù)資料
型號： 3D7303K-300
廠商： DATA DELAY DEVICES INC
元件分類： 通用總線功能
英文描述： MONOLITHIC TRIPLE FIXED DELAY LINE
中文描述： SILICON DELAY LINE, TRUE OUTPUT, PDIP14
封裝： 0.300 INCH, DIP-14
文件頁數(shù)： 1/4頁
文件大?。?/td> 40K
代理商： 3D7303K-300
3D7303
Doc #96001
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
MONOLITHIC TRIPLE
FIXED DELAY LINE
(SERIES 3D7303)
FEATURES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
10 through 500ns
Delay tolerance:
2% or 1.0ns
Temperature stability:
±
3% typical (0C-70C)
Vdd stability:
±
1% typical (4.75V-5.25V)
Minimum input pulse width:
20% of total
delay
14-pin DIP available as drop-in replacement for
hybrid delay lines
FUNCTIONAL DESCRIPTION
The 3D7303 Triple Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains three matched,
independent delay lines. Delay values can range from 10ns through
500ns. The input is reproduced at the output without inversion,
shifted in time as per the user-specified dash number. The 3D7303
is TTL- and CMOS-compatible, capable of driving ten 74LS-type
loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7303 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
data
delay
devices,
inc.
3
PACKAGES
8
7
6
5
1
2
3
4
I1
I2
I3
GND
VDD
O1
O2
O3
3D7303M DIP
3D7303H Gull-Wing
(300 Mil)
1
2
3
4
8
7
6
5
I1
I2
I3
GND
VDD
O1
O2
O3
3D7303Z SOIC
(150 Mil)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
I1
N/C
I2
N/C
I3
N/C
GND
VDD
N/C
O1
N/C
O2
N/C
O3
3D7303
3D7303G Gull-Wing
3D7303K Unused pins
removed
(300 Mil)
DIP
PIN DESCRIPTIONS
I1
I2
I3
O1
O2
O3
VCC
GND
N/C
Delay Line 1 Input
Delay Line 2 Input
Delay Line 3 Input
Delay Line 1 Output
Delay Line 2 Output
Delay Line 3 Output
+5 Volts
Ground
No Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
SOIC-8
3D7303Z
DELAY
PER LINE
(ns)
INPUT RESTRICTIONS
Absolute Max
Oper. Freq.
DIP-8
3D7303M
3D7303H
-10
-15
-20
-25
-30
-40
-50
-100
-200
-300
-400
-500
DIP-14
3D7303
3D7303G
-10
-15
-20
-25
-30
-40
-50
-100
-200
-300
-400
-500
DIP-14
3D7303K
Max Operating
Frequency
Min Operating
Pulse Width
Absolute Min
Oper. P.W.
-10
-15
-20
-25
-30
-40
-50
-100
-200
-300
-400
-500
-10
-15
-20
-25
-30
-40
-50
-100
-200
-300
-400
-500
10
±
1.0
15
±
1.0
20
±
1.0
25
±
1.0
30
±
1.0
40
±
1.0
50
±
1.0
100
±
2.0
200
±
4.0
300
±
6.0
400
±
8.0
500
±
10.0
33.3 MHz
22.2 MHz
16.7 MHz
13.3 MHz
11.1 MHz
8.33 MHz
6.67 MHz
3.33 MHz
1.67 MHz
1.11 MHz
0.83 MHz
0.67 MHz
100.0 MHz
100.0 MHz
100.0 MHz
83.3 MHz
71.4 MHz
62.5 MHz
50.0 MHz
25.0 MHz
12.5 MHz
8.33 MHz
6.25 MHz
5.00 MHz
15.0 ns
22.5 ns
30.0 ns
37.5 ns
45.0 ns
60.0 ns
75.0 ns
150.0 ns
300.0 ns
450.0 ns
600.0 ns
750.0 ns
5.0 ns
5.0 ns
5.0 ns
6.0 ns
7.0 ns
8.0 ns
10.0 ns
20.0 ns
40.0 ns
60.0 ns
80.0 ns
100.0 ns
NOTE:
Any delay between 10 and 500 ns not shown is also available.
1996 Data Delay Devices
相關(guān)PDF資料
PDF描述
3D7303SERIES 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
3D7303 MONOLITHIC TRIPLE FIXED DELAY LINE
3D7304D-10 MONOLITHIC QUADRUPLE FIXED DELAY LINE
3D7304 MONOLITHIC QUADRUPLE FIXED DELAY LINE
3D7304SERIES MONOLITHIC QUADRUPLE FIXED DELAY LINE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
3D7303K40 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC
3D7303K-40 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE
3D7303K400 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC
3D7303K-400 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE
3D7303K50 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC
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