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參數(shù)資料
| 型號： | 3D7323G-1000 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, PDSO14 |
| 封裝： | ROHS COMPLIANT, GULL-WING, DIP-14 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 139K |
| 代理商： | 3D7323G-1000 |
Doc #06015
5/10/2006
3D7323
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
APPLICATION NOTES (CONT’D)
custom reference designator
identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7323 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The
thermal coefficient
is reduced to
300
PPM/C
, which is equivalent to a variation , over
the -40C to 85C operating range, of
±
3%
from
the room-temperature delay settings and/or
1.0ns
, whichever is greater. The
power supply
coefficient
is reduced, over the 4.75V to 5.25V
operating range, to
±
1%
of the delay settings at
the nominal 5.0VDC power supply and/or
2.0ns
,
whichever is greater.
It is essential that the
power supply pin be
adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
DC Supply Voltage
V
DD
Input Pin Voltage
V
IN
Input Pin Current
I
IN
Storage Temperature
T
STRG
Lead Temperature
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
Static Supply Current*
I
DD
High Level Input Voltage
V
IH
Low Level Input Voltage
V
IL
High Level Input Current
I
IH
Low Level Input Current
I
IL
High Level Output Current
I
OH
MIN
2.0
-1
-1
MAX
5
0.8
1
1
-4.0
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
Low Level Output Current
I
OL
4.0
mA
Output Rise & Fall Time
T
R
& T
F
2
ns
*I
DD
(Dynamic) = 3 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 3D7324-40 | MONOLITHIC QUADRUPLE FIXED DELAY LINE |
| 3D7408-0.25 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408SERIES | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-0.5 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7323G-15 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323G-20 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323G-200 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323G-25 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323G-30 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
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