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參數(shù)資料
| 型號(hào)： | 3D7418-0.25 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 中文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDIP16 |
| 封裝： | DIP-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 171K |
| 代理商： | 3D7418-0.25 |
3D7418
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7418 – LOW NOISE)
FEATURES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Increment range:
0.25 through 5.0ns
Delay tolerance:
1% (See Table 1)
Temperature stability:
±
3% typical (0C-70C)
Vdd stability:
±
1% typical (4.75V-5.25V)
Minimum input pulse width:
10% of total
delay
Programmable via 3-wire serial or 8-bit
parallel interface
FUNCTIONAL DESCRIPTION
The 3D7418 Programmable 8-Bit Silicon Delay Line product family
consists of 8-bit, user-programmable CMOS silicon integrated
circuits. Delay values, programmed either via the serial or parallel
interface, can be varied over 255 equal steps ranging from 250ps
to 5.0ns inclusively. Units have a typical inherent (zero step)
delay of 12ns to 17ns (See Table 1). The input is reproduced at
the output without inversion, shifted in time as per user selection.
The 3D7418 is TTL- and CMOS-compatible, capable of driving ten
74LS-type loads, and features both rising- and falling-edge
accuracy.
The all-CMOS 3D7418 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.
PACKAGES
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN
AE
SO/P0
P1
P2
P3
P4
GND
VDD
OUT
MD
P7
P6
SC
P5
SI
3D7418
3D7418G Gull Wing
DIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
AE
SO/P0
P1
P2
P3
P4
GND
VDD
OUT
MD
P7
P6
SC
P5
SI
3D7418S SOL
(300 Mil)
PIN DESCRIPTIONS
IN
Signal Input
OUT
Signal Output
MD
Mode Select
AE
Address Enable
P0-P7 Parallel Data Input
SC
Serial Clock
SI
Serial Data Input
SO
Serial Data Output
VDD
+5 Volts
GND
Ground
TABLE 1: PART NUMBER SPECIFICATIONS
DELAYS AND TOLERANCES
Step 0
Delay (ns)
Delay (ns)
Increment (ns)
12
±
2
75.75
±
4.0
0.25
±
0.15
12
±
2
139.5
±
4.0
0.50
±
0.25
12
±
2
267.0
±
5.0
1.00
±
0.50
14
±
2
522.0
±
6.0
2.00
±
1.00
17
±
2
782.0
±
8.0
3.00
±
1.50
17
±
2
1037
±
9.0
4.00
±
2.00
17
±
2
1292
±
10
5.00
±
2.50
PART
NUMBER
INPUT RESTRICTIONS
Absolute Max
Oper Freq
90 MHz
45 MHz
22 MHz
11 MHz
7.5 MHz
5.5 MHz
4.4 MHz
Step 255
Delay
Max Operating
Frequency
6.25 MHz
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
Min Operating
P.W.
Absolute Min
Oper P.W.
3D7418-0.25
3D7418-0.5
3D7418-1
3D7418-2
3D7418-3
3D7418-4
3D7418-5
80.0 ns
160.0 ns
320.0 ns
640.0 ns
960.0 ns
1280.0 ns
1600.0 ns
5.5 ns
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
110.0 ns
NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.
All delays referenced to input pin
2002 Data Delay Devices
For mechanical dimensions, click
here
.
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7418-1 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 3D7418-2 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 3D7418-3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 3D7418-4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 3D7418-5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
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