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參數(shù)資料
| 型號(hào)： | 3D7428 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 中文描述： | 整體式8位可編程延遲線 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 513K |
| 代理商： | 3D7428 |
3D7428
APPLICATION NOTES (CONT’D)
LATCHED PARALLEL MODE
(MD = 1, AE PULSED)
The eight program pins P0 - P7 are loaded by the
falling edge of the Enable pulse, as shown in
Figure 3. After each change in delay value, a
settling time
t
EDV
is required before the input is
accurately delayed.
SERIAL MODE (MD = 0)
While observing data setup (
t
DSC
) and data hold
(
t
DHC
) requirements, timing data is loaded in
MSB-to-LSB order by the rising edge of the clock
(SC) while the enable (AE) is high, as shown in
Figure 4. The falling edge of the enable (AE)
activates the new delay value which is reflected
at the output after a settling time
t
EDV
. As data is
shifted into the serial data input (SI), the previous
contents of the 8-bit input register are shifted out
of the serial output port pin (SO) in MSB-to-LSB
order, thus allowing cascading of multiple
devices by connecting the serial output pin (SO)
of the preceding device to the serial data input
pin (SI) of the succeeding device, as illustrated in
Figure 5. The total number of serial data bits in a
cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
To initiate a serial read, enable (AE) is driven
high. After a time
t
EQV
, bit 7 (MSB) is valid at the
serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
The SO pin, if unused, must be allowed to float if
the device is configured in the serial
programming mode.
The serial mode is the only mode available on
the 8-pin version of the 3D7428.
PROGRAMMABLE
DELAY LINE
LATCH
8-BIT INPUT
REGISTER
MD
SC
SI
AE
IN
SO
OUT
P0 P1
P2
P3
P4
P5
P6
P7
MODE SELECT
SHIFT CLOCK
SERIAL INPUT
ADDRESS ENABLE
SIGNAL IN
SIGNAL OUT
SERIAL OUTPUT
PARALLEL INPUTS
Figure1: Functional block diagram
PREVIOUS
PREVIOUS
NEW VALUE
NEW VALUE
t
PDX
t
PDV
PARALLEL
INPUTS
P0-P7
DELAY
TIME
Figure 2: Non-latched parallel mode (MD=1, AE=1)
Doc #03003
11/1/04
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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| 3D7428-1 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7428-1.5 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7444-1.5 | MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7428_06 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7428-0.25 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7428-0.5 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7428-1 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7428-1.5 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
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