參數(shù)資料
型號(hào): 3D7444-1.5
廠商: DATA DELAY DEVICES INC
元件分類: 通用總線功能
英文描述: MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444)
中文描述: SILICON DELAY LINE, TRUE OUTPUT, PDIP14
封裝: DIP-14
文件頁數(shù): 6/6頁
文件大?。?/td> 157K
代理商: 3D7444-1.5
3D7444
Doc #03006
12/8/03
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (VDD):
5.0V
±
0.1V
Input Pulse:
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
OUTPUT:
R
load
:
C
load
:
Threshold:
1.65V (Rising & Falling)
10K
±
10%
5pf
±
10%
High = 3.3V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
3.0 ns Max. (measured
between 0.6V and 2.7V )
PW
IN
= 1.25 x Total Delay
PER
IN
= 2.5 x Total Delay
10K
470
5pf
Device
Under
Test
Digital
Scope
OUT1
OUT2
OUT3
OUT4
OUT
TRIG
IN
REF
TRIG
Figure 4: Test Setup
DEVICE UNDER
TEST (DUT)
DIGITAL SCOPE/
TIME INTERVAL COUNTER
PULSE
GENERATOR
IN4
COMPUTER
SYSTEM
PRINTER
IN3
IN2
IN1
Figure 5: Timing Diagram
t
PLH
t
PHL
PER
IN
PW
IN
t
RISE
t
FALL
0.6V
0.6V
2.7V
2.7V
1.65V
1.65V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
DATA DELAY DEVICES, INC.
6
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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