- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358638 > 3D7501G (Electronic Theatre Controls, Inc.) MONOLITHIC MANCHESTER ENCODER PDF資料下載
參數(shù)資料
| 型號： | 3D7501G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC MANCHESTER ENCODER |
| 中文描述： | 整裝曼徹斯特編碼 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 34K |
| 代理商： | 3D7501G |
3D7501
Doc #96010
5/19/97
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
The 3D7501 Manchester Encoder samples the
data input at the rising edge of the input clock.
The sampled data is used in conjunction with the
clock rising and falling edges to generate the by-
phase level Manchester code.
INPUT SIGNAL CHARACTERISTICS
The 3D7501 Manchester Encoder inputs
are
TTL compatible. The user should assure
himself that
the 1.5 volt TTL threshold is used
when referring to all timing, especially to the
input clock duty cycle.
CLOCK DUTY CYCLE ERRORS
The 3D7501 Manchester Encoder employs the
timing of the clock rising and falling edges (duty
cycle) to implement the required coding scheme.
To reduce the difference between the output data
high time and low time, it is essential that the
deviation of the input clock duty cycle from 50/50
be minimized.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7501 presents at its outputs the true and
the complimented encoded data.
The High-to-Low time skew of the selected data
output should be budgeted by the user, as it
relates to his application, to satisfactorily
estimate the distortion of the transmitted data
stream.
Such estimate is very useful in determining the
functionality and margins of the data link, if a
3D7502 Manchester Decoder is used to decode
the received data.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D7501 Manchester encoder utilizes
novel and innovative compensation circuitry to
minimize timing variations induced by
fluctuations in power supply and/or temperature.
RESET
(RESB)
CLOCK
(CIN)
DATA
(DIN)
TRANSMIT
(TX)
TRANSMIT
(TXB)
t
DS
t
DH
Figure 1: Timing Diagram
1/f
C
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
0
Power-on reset (Left high for normal operation)
T
2H
T
2L
T
1H
T
1L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 3D7501H | MONOLITHIC MANCHESTER ENCODER |
| 3D7501M | MONOLITHIC MANCHESTER ENCODER |
| 3D7501SERIES | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 3D7502 | MONOLITHIC MANCHESTER DECODER |
| 3D7502-10 | MONOLITHIC MANCHESTER DECODER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7501H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MONOLITHIC MANCHESTER ENCODER |
| 3D7501M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MONOLITHIC MANCHESTER ENCODER |
| 3D7501SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MONOLITHIC MANCHESTER ENCODER |
| 3D7501Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MONOLITHIC MANCHESTER ENCODER |
| 3D7502 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER DECODER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。