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參數(shù)資料
| 型號(hào)： | 3D7503-20 |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC MANCHESTER ENCODER/DECODER |
| 中文描述： | 整體式曼徹斯特編碼/解碼器 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大小： | 47K |
| 代理商： | 3D7503-20 |
3D7503
Doc #98009
12/11/98
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-10
-55
MAX
7.0
V
DD
+0.3
10
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
MIN
MAX
40
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
2.0
0.8
1.0
1.0
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
-4.0
Low Level Output Current
I
OL
4.0
mA
Output Rise & Fall Time
T
R
& T
F
2
ns
*I
DD
(Dynamic) = 2 * C
LD
* V
DD
* F
where:
C
= Average capacitance load/pin (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V, except as noted)
PARAMETER
Input Baud Rate (Encoder)
Clock Frequency
Data set-up to clock rising
Data hold from clock rising
TX High-Low time skew
TXB High-Low time skew
TX - TXB High/Low time skew
Nominal Input Baud Rate (Decoder)
Allowed Input Baud Rate Deviation
Allowed Input Baud Rate Deviation
SYMBOL
f
BN
f
C
t
DS
t
DH
t
1H
- t
1L
t
2H
- t
2L
t
1H
- t
2L
f
BN
f
B
f
B
MIN
TYP
MAX
50
50
UNITS
MBaud
MHz
ns
ns
ns
ns
ns
MBaud
MBaud
MBaud
NOTES
3.5
0
-3.5
-2.0
-3.0
5
3.5
2.0
3.0
50
1
1
1
-0.15 f
BN
-0.05 f
BN
0.15 f
BN
0.05 f
BN
25C, 5.00V
-40C to 85C
4.75V to 5.25V
-55C to 125C
4.75V to 5.25V
Allowed Input Baud Rate Deviation
f
B
-0.03 f
BN
0.03 f
BN
MBaud
Allowed Input Duty Cycle
Bit Cell Time
Input Data Edge to Clock Falling Edge
Clock Width Low
Clock Falling Edge to Data Transition
42.5
50.0
1000/f
B
0.75 tc
500/f
BN
4.0
57.5
%
ns
ns
ns
ns
tc
t
CL
t
CWL
t
CD
±
2ns or 5%
3.0
5.0
Notes: 1: Assumes a 50% duty cycle clock input
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|---|---|
| 3D7503-25 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7503-30 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7503-40 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7503-5 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7503-50 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
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