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參數(shù)資料
| 型號(hào)： | 3D7523-0.5 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | MONOLITHIC MANCHESTER ENCODER/DECODER |
| 中文描述： | DATACOM, MANCHESTER ENCODER/DECODER, PDIP14 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, DIP-14 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | 3D7523-0.5 |
3D7523
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DC Supply Voltage
VDD
-0.3
7.0
V
Input Pin Voltage
VIN
-0.3
VDD+0.3
V
Input Pin Current
IIN
-10
10
mA
25C
Storage Temperature
TSTRG
-55
150
C
Lead Temperature
TLEAD
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Static Supply Current*
IDD
5
mA
High Level Input Voltage
VIH
2.0
V
Low Level Input Voltage
VIL
0.8
V
High Level Input Current
IIH
1.0
A
VIH = VDD
Low Level Input Current
IIL
1.0
A
VIL = 0V
High Level Output Current
IOH
-4.0
mA
VDD = 4.75V
VOH = 2.4V
Low Level Output Current
IOL
4.0
mA
VDD = 4.75V
VOL = 0.4V
Output Rise & Fall Time
TR & TF
2
ns
CLD = 5 pf
*IDD(Dynamic) = 2 * CLD * VDD * F
Input Capacitance = 10 pf typical
where: CLD = Average capacitance load/pin (pf)
Output Load Capacitance (CLD) = 25 pf max
F = Input frequency (GHz)
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V, except as noted)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Baud Rate (Encoder)
fBN
50
MBaud
Clock Frequency
fC
50
MHz
Data set-up to clock rising
tDS
3.5
ns
Data hold from clock rising
tDH
0
ns
TX High-Low time skew
t1H - t1L
-3.5
3.5
ns
1
TXB High-Low time skew
t2H - t2L
-2.0
2.0
ns
1
TX - TXB High/Low time skew
t1H - t2L
-3.0
3.0
ns
1
Nominal Input Baud Rate (Decoder)
fBN
5
50
MBaud
Allowed Input Baud Rate Deviation
fB
-0.15 fBN
0.15 fBN
MBaud
0C to 70C
25C, 5.00V
Allowed Input Baud Rate Deviation
fB
-0.05 fBN
0.05 fBN
MBaud
4.75V to 5.25V
Allowed Input Baud Rate Deviation
fB
-0.03 fBN
0.03 fBN
MBaud
-55C to 125C
4.75V to 5.25V
Allowed Input Duty Cycle
42.5
50.0
57.5
%
Bit Cell Time
tc
1000/fB
ns
Input Data Edge to Clock Falling Edge
tCL
0.75 tc
ns
Clock Width Low
tCWL
500/fBN
ns
±2ns or 5%
Clock Falling Edge to Data Transition
tCD
3.0
4.0
5.0
ns
Notes: 1: Assumes a 50% duty cycle clock input
Doc #06003
DATA DELAY DEVICES, INC.
4
5/8/2006
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7523-1 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523-10 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523-20 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523-25 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
| 3D7523-5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC MANCHESTER ENCODER/DECODER |
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