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參數(shù)資料
| 型號(hào)： | 3D7622 |
| 廠商： | Data Delay Devices, Inc. |
| 英文描述： | 22-BIT PROGRAMMABLE PULSE GENERATOR |
| 中文描述： | 22位可編程脈沖發(fā)生器 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大小： | 186K |
| 代理商： | 3D7622 |
3D7622
APPLICATION NOTES (CONT’D)
TRIGGER & RESET TIMING
Figure 2 shows the timing diagram of the device
when the reset input (RES) is not used. In this
case, the pulse is triggered by the rising edge of
the TRIG signal and ends at a time determined
by the address loaded into the device. While the
pulse is active, any additional triggers occurring
are ignored. Once the pulse has ended, and after
a short recovery time, the next trigger is
recognized. Figure 3 shows the timing for the
case where a reset is issued before the pulse
has ended. Again, there is a short recovery time
required before the next trigger can occur.
ADDRESS UPDATE
While observing data setup (t
DS
) and data hold
(t
DH
) requirements, timing data is loaded in MSB-
to-LSB order by the rising edge of the clock (SC)
while the enable (AE) is high, as shown in Figure
4. The falling edge of the AE activates the new
pulse width value, which is reflected at the output
upon the next trigger.
As shown in the figure, most of the address
information for the next pulse can be loaded
while the current pulse is active. It is only on the
falling-edge of AE that the device adjusts to the
new pulse width setting. In other words, the
device controller does not need to wait for the
current pulse to end before beginning an address
update sequence. This can save a considerable
amount of time in certain applications.
As data is shifted into the serial data input (SI),
the previous contents of the 22-bit input register
are shifted out of the serial output pin (SO) in
MSB-to-LSB order. This allows cascading of
multiple devices by connecting SO of the
preceding device to SI of the succeeding device,
as illustrated in Figure 5. The total number of
serial data bits in a cascade configuration must
be 22 times the number of units, and each group
of 22 bits must be transmitted in MSB-to-LSB
order.
22-BIT LATCH
22-BIT INPUT
REGISTER
SC
SI
AE
TRG
SO
SERIAL CLK
SERIAL IN
ADDR ENABLE
TRIGGER
PULSE OUT
SERIAL OUT
Figure 1: Functional block diagram
OUT
OUTB
RES
RESET
16
MSB
6
LSB
DELAY
LINE
OSCILLATOR/
COUNTER
INPUT
LOGIC
OUTPUT
LOGIC
Doc #06007
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 3D7622D-0.25 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:22-BIT PROGRAMMABLE PULSE GENERATOR |
| 3D7622D-0.4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:22-BIT PROGRAMMABLE PULSE GENERATOR |
| 3D7622D-0.5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:22-BIT PROGRAMMABLE PULSE GENERATOR |
| 3D7622D-1 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:22-BIT PROGRAMMABLE PULSE GENERATOR |
| 3D7622D-10 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:22-BIT PROGRAMMABLE PULSE GENERATOR |
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