- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄351989 > 4605X-101-222 Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits PDF資料下載
參數(shù)資料
| 型號： | 4605X-101-222 |
| 英文描述： | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 中文描述： | WIDERSTAND NETZWERK DICKFILM 2K2 5ST |
| 文件頁數(shù)： | 51/62頁 |
| 文件大?。?/td> | 1883K |
| 代理商： | 4605X-101-222 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
Specifications are subject to change without notice.
331
Use Bourns Networks To:
Match impedance between memory driver and the DRAM
array.
Minimize reflections and ringing in DRAM inputs.
Prevent undershoot of RAS, CAS, and WE signals which
may result in latch-up of DRAM inputs
Improve system performance by allowing faster setting
times for DRAM inputs.
Need For Damping
The address lines (RAS, CAS) and control lines (WE) of
dynamic RAM arrays are driven in parallel, causing significant
loading on the driver of the DRAM arrays. Each DRAM control
input (WE) has capacitive loading between 5pF to 7pF, while
each address line input has about a 10pF load.
Thus each DRAM input can be modeled as a transmission line
with distributed inductance and capacitance. If not properly ter-
minated, signal reflections and ringing on the line will result,
adversely affecting the performance of the memory system. The
effects on signal transitions will be:
1. Increased settling time delay on low-to-high transitions.
2. Voltage undershoot on high-to-low transitions.
Increased settling time due to ringing reduces system perfor-
mance because the design has to allow for the settling delay
before sampling the signal. Undershoot, by bringing the input
voltage below 0 volts, can damage the driver IC as well as alter
the DRAM’s internal address register contents, causing potential
loss of data.
TIMING
REFERENCE
MEMORY
CONTROL
DATA
SYSTEM DATA BUS
TIMING
CONTROLLERS
DATA
CPU
ADDRESS
DYNAMIC
MEMORY
CONTROL
ADDRESS
RAS
CAS
WE
DYNAMIC
MEMORY
ARRAY
BLOCK DIAGRAM OF DRAM SYSTEM
EFFECT OF DAMPING RESISTOR
WITHOUT
DAMPING
RESISTOR
WITH
DAMPING
RESISTOR
Courtesy of B. Narasimhan and J. Shaffer, Micron Techology Corporation.
t1
t2
1
V
"HIGH"
LOGIC
LEVEL
COMPARISON OF UNDERSHOOTS
WITHOUT
DAMPING RESISTOR
WITH
DAMPING RESISTOR
t1 - TIME TO ACCEPTABLE "LOW" LOGIC LEVEL FOR
DRIVER WITHOUT DAMPING RESISTOR
t2 - TIME TO ACCEPTABLE "LOW" LOGIC
LEVEL WITHDAMPING RESISTOR
DRAM Applications
相關PDF資料 |
PDF描述 |
|---|---|
| 4605X-101-223 | WIDERSTAND NETZWERK DICKFILM 22K 5ST |
| 4605X-101-472 | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 4607X102 | Interface IC |
| 4607X103 | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 4607X104 | Interface IC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 4605X-101-222F | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:4600X Series - Thick Film Conformal SIPs |
| 4605X-101-222LF | 功能描述:電阻器網(wǎng)絡與陣列 5pins 2.2Kohms Bussed RoHS:否 制造商:Vishay/Thin Film 產(chǎn)品類型:Networks 電路類型:Divider 電阻器數(shù)量: 電阻數(shù)值:10 kOhms 容差:0.1 % 溫度系數(shù): 管腳數(shù)量:3 工作溫度范圍:- 55 C to + 155 C 尺寸:1.02 mm W x 3.05 mm L x 1.4 mm H 引線間隔: 端接類型:SMD/SMT 封裝:Reel |
| 4605X-101-222LF | 制造商:Bourns Inc 功能描述:RESISTORS NETWORKS THICK FILM NETWORK C |
| 4605X-101-223 | 功能描述:電阻器網(wǎng)絡與陣列 2.2K 5Pin Bussed RoHS:否 制造商:Vishay/Thin Film 產(chǎn)品類型:Networks 電路類型:Divider 電阻器數(shù)量: 電阻數(shù)值:10 kOhms 容差:0.1 % 溫度系數(shù): 管腳數(shù)量:3 工作溫度范圍:- 55 C to + 155 C 尺寸:1.02 mm W x 3.05 mm L x 1.4 mm H 引線間隔: 端接類型:SMD/SMT 封裝:Reel |
| 4605X-101-223LF | 功能描述:電阻器網(wǎng)絡與陣列 5pins 22Kohms Bussed RoHS:否 制造商:Vishay/Thin Film 產(chǎn)品類型:Networks 電路類型:Divider 電阻器數(shù)量: 電阻數(shù)值:10 kOhms 容差:0.1 % 溫度系數(shù): 管腳數(shù)量:3 工作溫度范圍:- 55 C to + 155 C 尺寸:1.02 mm W x 3.05 mm L x 1.4 mm H 引線間隔: 端接類型:SMD/SMT 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。