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參數(shù)資料
| 型號： | 4609X-101-103 |
| 英文描述： | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 中文描述： | WIDERSTAND NETZWERK DICKFILM 10,000 5ST |
| 文件頁數(shù)： | 51/62頁 |
| 文件大?。?/td> | 1883K |
| 代理商： | 4609X-101-103 |
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Specifications are subject to change without notice.
331
Use Bourns Networks To:
Match impedance between memory driver and the DRAM
array.
Minimize reflections and ringing in DRAM inputs.
Prevent undershoot of RAS, CAS, and WE signals which
may result in latch-up of DRAM inputs
Improve system performance by allowing faster setting
times for DRAM inputs.
Need For Damping
The address lines (RAS, CAS) and control lines (WE) of
dynamic RAM arrays are driven in parallel, causing significant
loading on the driver of the DRAM arrays. Each DRAM control
input (WE) has capacitive loading between 5pF to 7pF, while
each address line input has about a 10pF load.
Thus each DRAM input can be modeled as a transmission line
with distributed inductance and capacitance. If not properly ter-
minated, signal reflections and ringing on the line will result,
adversely affecting the performance of the memory system. The
effects on signal transitions will be:
1. Increased settling time delay on low-to-high transitions.
2. Voltage undershoot on high-to-low transitions.
Increased settling time due to ringing reduces system perfor-
mance because the design has to allow for the settling delay
before sampling the signal. Undershoot, by bringing the input
voltage below 0 volts, can damage the driver IC as well as alter
the DRAM’s internal address register contents, causing potential
loss of data.
TIMING
REFERENCE
MEMORY
CONTROL
DATA
SYSTEM DATA BUS
TIMING
CONTROLLERS
DATA
CPU
ADDRESS
DYNAMIC
MEMORY
CONTROL
ADDRESS
RAS
CAS
WE
DYNAMIC
MEMORY
ARRAY
BLOCK DIAGRAM OF DRAM SYSTEM
EFFECT OF DAMPING RESISTOR
WITHOUT
DAMPING
RESISTOR
WITH
DAMPING
RESISTOR
Courtesy of B. Narasimhan and J. Shaffer, Micron Techology Corporation.
t1
t2
1
V
"HIGH"
LOGIC
LEVEL
COMPARISON OF UNDERSHOOTS
WITHOUT
DAMPING RESISTOR
WITH
DAMPING RESISTOR
t1 - TIME TO ACCEPTABLE "LOW" LOGIC LEVEL FOR
DRIVER WITHOUT DAMPING RESISTOR
t2 - TIME TO ACCEPTABLE "LOW" LOGIC
LEVEL WITHDAMPING RESISTOR
DRAM Applications
相關PDF資料 |
PDF描述 |
|---|---|
| 4609X-101-104 | WIDERSTAND NETZWERK DICKFILM 100K 5ST |
| 4609X-101-105 | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 4610M-901-103 | KONDENSATOR NETZWERK |
| 4610M-901-104 | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 4610M-902-103 | KONDENSATOR NETZWERK |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 4609X-101-103 | 制造商:Bourns Inc 功能描述:Resistor Network10kOhm2%Bussed+/-100 |
| 4609X-101-103F | 制造商:Bourns Inc 功能描述: |
| 4609X-101-103FLF | 制造商:Bourns / JW Miller 功能描述:Res Thick Film NET 10K Ohm 1% 1.13W 制造商:Bourns Inc 功能描述:RES THKFLM NET 10K OHM 1% 1.13W 100PPM/ C BUS 9SIP PIN TH - Bulk 制造商:Bourns Inc 功能描述:Res Thick Film NET 10K Ohm 1% 1.13W ±100ppm/°C BUS Conformal 9-Pin SIP Pin Thru-Hole Bulk 制造商:Bourns 功能描述:Res Thick Film NET 10K Ohm 1% 1.13W |
| 4609X-101-103LF | 功能描述:電阻器網(wǎng)絡與陣列 9pins 10Kohms Bussed RoHS:否 制造商:Vishay/Thin Film 產(chǎn)品類型:Networks 電路類型:Divider 電阻器數(shù)量: 電阻數(shù)值:10 kOhms 容差:0.1 % 溫度系數(shù): 管腳數(shù)量:3 工作溫度范圍:- 55 C to + 155 C 尺寸:1.02 mm W x 3.05 mm L x 1.4 mm H 引線間隔: 端接類型:SMD/SMT 封裝:Reel |
| 4609X-101-103LF | 制造商:Bourns Inc 功能描述:RESISTORS NETWORKS THICK FILM NETWORK C 制造商:Bourns Inc 功能描述:RESISTORS NETWORK THICK FILM 制造商:Bourns Inc 功能描述:RESISTORS, NETWORK, THICK FILM, 8X, 10K |
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