參數(shù)資料
型號(hào): 49FCT3805SOG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: FCT SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: GREEN, SOIC-20
文件頁(yè)數(shù): 6/7頁(yè)
文件大?。?/td> 68K
代理商: 49FCT3805SOG
6
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
IDT49FCT3805/A
3.3VCMOSBUFFER/CLOCKDRIVER
D.U.T.
VIN
VOUT
VCC
RT
Pulse
Generator
50pF
500
6V
GND
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
3V
1.5V
0V
3.5V
0V
SWITCH
CLOSED
SWITCH
OPEN
V OL
VOH
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
3V
0V
VOH
tPLH
tPHL
VOL
1.5V
tR
tF
2.0V
0.8V
INPUT
OUTPUT
tPLH
tPHL
3V
0V
VOH
1.5V
VOL
tSK(p) = |tPHL - tPLH|
INPUT
OUTPUT
tPLH1
OUTPUT 1
OUTPUT 2
tSK(o)
tPLH2
3V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
INPUT
tPHL1
tPHL2
tSK(o)
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
INPUT
tPLH1
PACKAGE 1
OUTPUT
tSK(t)
tPLH2
3V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tPHL1
tPHL2
tSK(t)
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
PACKAGE 2
OUTPUT
Package Delay
TEST CIRCUITS AND WAVEFORMS
Pulse Skew - tSK(P)
Test Circuits for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test
Switch
Disable LOW
6V
Enable LOW
Disable HIGH
GND
Enable HIGH
SWITCH POSITION
Output Skew - tSK(X)
Output Skew - tSK(O)
Package Skew - tSK(T)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f
≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns
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