參數(shù)資料
型號(hào): 514JBAXXXXXXAAG
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 250 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝: 5 X 7 MM, ROHS COMPILANT PACKAGE-6
文件頁(yè)數(shù): 29/32頁(yè)
文件大?。?/td> 267K
代理商: 514JBAXXXXXXAAG
Si514
6
Preliminary Rev. 0.9
Table 4. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
CMOS Output Logic
High
VOH
0.85 x VDD
——
V
CMOS Output Logic
Low
VOL
0.15 x VDD
V
CMOS Output Logic
High Drive
IOH
3.3 V
–8
mA
2.5 V
–6
mA
1.8 V
–4
mA
CMOS Output Logic
Low Drive
IOL
3.3 V
8
mA
2.5 V
6
mA
1.8 V
4
mA
CMOS Output
Rise/Fall Time
(20 to 80% VDD)
TR/TF
0.1 to 125 MHz,
CL = 15 pF
——
1.9
ns
0.1 to 212.5 MHz,
CL = no load
—1.0
ns
LVPECL/HCSL Out-
put Rise/Fall Time
TR/TF
——
520
ps
LVDS Output Rise/Fall
Time
TR/TF
——
800
ps
LVPECL Output Com-
mon Mode
VOC
50
to VDD – 2 V, single-ended
VDD
1.4 V
—V
LVPECL Output Swing
VO
50
to VDD – 2 V, single-ended
0.55
0.8
0.95
VPPSE
LVDS Output Common
Mode
VOC
100
line-line, 3.3/2.5 V
1.13
1.20
1.28
V
100
line-line, 1.8 V
0.83
0.90
0.97
V
LVDS Output Swing
VO
Single-ended 100
differential
termination
0.25
0.35
0.45
VPPSE
HCSL Output
Common Mode
VOC
50
to ground
0.35
0.38
0.40
V
HCSL Output Swing
VO
Single-ended
0.58
0.73
0.85
VPPSE
Duty Cycle
DC
455055
%
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