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參數(shù)資料
| 型號(hào)： | 514PCBXXXXXXBAG |
| 廠商： | SILICON LABORATORIES |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 170 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 封裝： | 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6 |
| 文件頁(yè)數(shù)： | 28/32頁(yè) |
| 文件大小： | 267K |
| 代理商： | 514PCBXXXXXXBAG |
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Si514
Preliminary Rev. 0.9
5
Table 3. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Programmable
Frequency Range
FO
CMOS
0.100
—
212.5
MHz
FO
LVDS/LVPECL/HCSL
0.100
—
250
MHz
Frequency
Reprogramming
Resolution
MRES
—
0.026
—
ppb
Frequency Range for
Small Frequency Change
(Continuous Glitchless
Output)
From center frequency
–1000
—
+1000
ppm
Settling time for Small
Frequency Change
<±1000 ppm from
center frequency
—
100
s
Settling time for Large
Frequency Change (Out-
put Squelched during Fre-
quency Transition)
>±1000 ppm from
center frequency
——
10
ms
Total Stability
Frequency Stability Grade C1
–30
—
+30
ppm
Frequency Stability Grade B2
–50
—
+50
ppm
Frequency Stability Grade A2
–100
—
+100
ppm
Temperature Stability
Frequency Stability Grade C
–20
—
+20
ppm
Frequency Stability Grade B
–25
—
+25
ppm
Frequency Stability Grade A
–50
—
+50
ppm
Startup Time
TSU
Minimum VDD until output
frequency (FO) within specification
——
10
ms
Disable Time
TD
FO < 10 MHz
—
60
s
FO 10 MHz
—
25
s
Notes:
1.
Total stability includes initial accuracy, operating temperature, supply voltage change, load change, and shock and
vibration (not under operation), and 1 year aging at 25 oC.
2.
Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration
(not under operation), and 10 years aging at 40 oC.
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