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參數(shù)資料
| 型號(hào)： | 530AA1362M00DGR |
| 廠(chǎng)商： | SILICON LABORATORIES |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 1362 MHz, LVPECL OUTPUT |
| 封裝： | ROHS COMPLIANT, SMD, 6 PIN |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | 530AA1362M00DGR |
Si530/531
4
Rev. 1.1
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)*
for FOUT > 500 MHz
φ
J
12 kHz to 20 MHz (OC-48)
—
0.25
0.40
ps
50 kHz to 80 MHz (OC-192)
—
0.26
0.37
Phase Jitter (RMS)*
for FOUT of 125 to 500 MHz
φ
J
12 kHz to 20 MHz (OC-48)
—
0.36
0.50
ps
50 kHz to 20 MHz (OC-192)
—
0.34
0.42
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter*
JPER
RMS
—
2
—
ps
Peak-to-Peak
—
14
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Offset Frequency (f)
120.00 MHz
LVDS
156.25 MHz
LVPECL
622.08 MHz
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–112
–122
–132
–137
–144
–150
n/a
–105
–122
–128
–135
–144
–147
n/a
–97
–107
–116
–121
–134
–146
–148
dBc/Hz
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