參數(shù)資料
          型號: 530UA667M000DGR
          廠商: SILICON LABORATORIES
          元件分類: XO, clock
          英文描述: CRYSTAL OSCILLATOR, CLOCK, 667 MHz, CMOS/TTL OUTPUT
          封裝: ROHS COMPLIANT, SMD, 6 PIN
          文件頁數(shù): 1/12頁
          文件大?。?/td> 215K
          代理商: 530UA667M000DGR
          Rev. 1.1 6/07
          Copyright 2007 by Silicon Laboratories
          Si530/531
          CRYSTAL OSCILLATOR (XO)
          (10 MHZ TO 1.4 GHZ)
          Features
          Applications
          Description
          The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
          to provide a low jitter clock at high frequencies. The Si530/531 is available
          with any-rate output frequency from 10 to 945 MHz and select frequencies to
          1400 MHz. Unlike a traditional XO, where a different crystal is required for
          each output frequency, the Si530/531 uses one fixed crystal to provide a
          wide range of output frequencies. This IC based approach allows the crystal
          resonator to provide exceptional frequency stability and reliability. In addition,
          DSPLL clock synthesis provides superior supply noise rejection, simplifying
          the task of generating low jitter clocks in noisy environments typically found in
          communication systems. The Si530/531 IC based XO is factory configurable
          for a wide variety of user specifications including frequency, supply voltage,
          output format, and temperature stability. Specific configurations are factory
          programmed at time of shipment, thereby eliminating long lead times
          associated with custom oscillators.
          Functional Block Diagram
          Available with any-rate output
          frequencies from 10 MHz to 945 MHz
          and select frequencies to 1.4 GHz
          3rd generation DSPLL with superior
          jitter performance
          3x better frequency stability than
          SAW-based oscillators
          Internal fixed crystal frequency
          ensures high reliability and low
          aging
          Available CMOS, LVPECL,
          LVDS, and CML outputs
          3.3, 2.5, and 1.8 V supply options
          Industry-standard 5 x 7 mm
          package and pinout
          Pb-free/RoHS-compliant
          SONET/SDH
          Networking
          SD/HD video
          Test and measurement
          Clock and data recovery
          FPGA/ASIC clock generation
          Fixed
          Frequency
          XO
          Any-rate
          10–1400 MHz
          DSPLL
          Clock
          Synthesis
          VDD
          CLK+
          CLK–
          OE
          GND
          Ordering Information:
          Pin Assignments:
          (Top View)
          Si5602
          1
          2
          3
          6
          5
          4
          GND
          OE
          VDD
          CLK+
          CLK–
          NC
          1
          2
          3
          6
          5
          4
          GND
          NC
          VDD
          CLK
          NC
          OE
          1
          2
          3
          6
          5
          4
          GND
          NC
          VDD
          CLK+
          CLK–
          OE
          Si530 (LVDS/LVPECL/CML)
          Si530 (CMOS)
          Si531 (LVDS/LVPECL/CML)
          REVISION D
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