參數(shù)資料
型號(hào): 54AC109
廠商: National Semiconductor Corporation
英文描述: Dual JK Positive Edge-Triggered Flip-Flop
中文描述: 雙JK上升沿觸發(fā)器
文件頁(yè)數(shù): 2/8頁(yè)
文件大小: 167K
代理商: 54AC109
Connection Diagrams
Truth Table
(each half)
Inputs
Outputs
S
D
C
D
CP
J
K
QQ
LH
X
H
L
HL
X
L
H
LL
X
H
HH
N
LL
L
H
HH
N
H
L
Toggle
HH
N
LH
Q
0
Q
0
HH
N
HH
H
L
HH
L
X
Q
0
Q
0
H = HIGH Voltage Level
L = LOW Voltage Level
N = LOW-to-HIGH Transition
X = Immaterial
Q0(Q0) = Previous Q0 (Q0) before LOW-to-HIGH Transition of Clock
Logic Diagram (one half shown)
Pin Assignment
for DIP and Flatpak
DS100267-3
Pin Assignment
for LCC
DS100267-4
DS100267-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
54AC109D 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Dual JK Positive Edge-Triggered Flip-Flop
54AC109DMQB 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:J-K-Type Flip-Flop
54AC109F 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Dual JK Positive Edge-Triggered Flip-Flop
54AC109FM 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC
54AC109FMQB 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:J-K-Type Flip-Flop