參數(shù)資料
型號(hào): 54F676FMQB
英文描述: SHIFT REGISTER|F-TTL|FP|24PIN|CERAMIC
中文描述: 移位寄存器|架F - TTL電|計(jì)劃生育| 24針|陶瓷
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 181K
代理商: 54F676FMQB
Logic Symbols
TL/F/9588–1
IEEE/IEC
TL/F/9588–4
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
b
1 mA/20 mA
HIGH/LOW
P
0
–P
15
CS
CP
M
SI
SO
Parallel Data Inputs
Chip Select Input (Active LOW)
Clock Pulse Input (Active LOW)
Mode Select Input
Serial Data Input
Serial Output
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Functional Description
The 16-bit shift register operates in one of three modes, as
indicated in the Shift Register Operations Table.
HOLDD
a HIGH signal on the Chip Select (CS) input pre-
vents clocking, and data is stored in the sixteen registers.
Shift/Serial LoadD
data present on the SI pin shifts into
the register on the falling edge of CP. Data enters the Q
0
position and shifts toward Q
15
on successive clocks, finally
appearing on the SO pin.
Parallel LoadD
data present on P
0
–P
15
are entered into
the register on the falling edge of CP. The SO output repre-
sents the Q
15
register output.
To prevent false clocking, CP must be LOW during a LOW-
to-HIGH transition of CS.
Shift Register Operations Table
Control Input
Operating Mode
CS
M
CP
H
L
L
X
L
H
X
Hold
Shift/Serial Load
Parallel Load
K
K
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
K
e
HIGH-to-LOW Transition
Block Diagram
TL/F/9588–5
2
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