參數(shù)資料
型號: 54FCT374ADB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20
封裝: CERAMIC, DIP-20
文件頁數(shù): 2/7頁
文件大小: 82K
代理商: 54FCT374ADB
MILITARYANDCOMMERCIAL TEMPERATURERANGES
2
IDT54/74FCT374/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
PIN CONFIGURATION
CERDIP/ SOIC
TOP VIEW
LCC
TOP VIEW
Symbol
Rating
Commercial
Military
Unit
VTERM(2)
Terminal Voltage
–0.5 to +7
V
with Respect to GND
VTERM(3)
Terminal Voltage
–0.5 to VCC
V
with Respect to GND
TA
Operating Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature under BIAS
–55 to +125
–65 to +135
°C
TSTG
Storage Temperature
–55 to +125
–65 to +150
°C
PT
Power Dissipation
0.5
W
IOUT
DC Output Current
120
mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
CAPACITANCE (TA= +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
1
2
3
4
5
7
9
6
8
10
11
12
13
14
15
16
17
18
19
20
O6
D7
D6
O5
D5
O
E
D
0
O
0
V
C
O
7
O
3
G
N
D
C
P
O
4
D
4
INDEX
D1
O1
D3
O2
D2
2
3
1
16
15
14
11
19
18
20
17
13
12
5
6
7
4
8
9
10
D1
O0
D0
VCC
O1
D3
O2
D2
O3
GND
O7
O6
D7
D6
O5
O4
D5
D4
CP
OE
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH transition
FUNCTION TABLE(1)
Inputs
Outputs
Internal
Function
OE
CP
Dx
Qx
High-Z
H
L
X
Z
N C
HH
X
Z
N C
Load
L
LL
H
Register
L
HH
L
H
LZ
H
HZ
L
Pin Names
Description
Dx
D flip-flop data inputs
C P
Clock Pulse for the register. Enters data on LOW-to-
HIGH transition.
Ox
3-State Outputs (TRUE)
O x
3-State Outputs (INVERTED)
OE
Active LOW 3-State Output Enable Input
PIN DESCRIPTION
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