- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄34466 > 550AE400M000BGR (SILICON LABORATORIES) VCXO, CLOCK, 400 MHz, LVPECL OUTPUT PDF資料下載
參數(shù)資料
| 型號(hào)： | 550AE400M000BGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 400 MHz, LVPECL OUTPUT |
| 封裝： | 5 X 7 MM, ROHS COMPLIANT PACKAGE-6 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 556K |
| 代理商： | 550AE400M000BGR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Si550
2
Rev. 0.5
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Voltage1
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
Supply Current
IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
120
108
99
90
130
117
108
98
mA
TriState mode
—
60
70
Output Enable (OE)2
VIH
0.75 x VDD
——
V
VIL
——
0.5
Operating Temperature Range3
TA
–40
—
85
C
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE pin includes a 17 k
pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
3. If the device is powered up below –20 C and the ambient temperature rises by approximately 105 C during normal
operation, the device will perform a one-time recalibration. The output is squelched for approximately 2–3 ms during
this recalibration.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope1,2,3
KV
10 to 90% of VDD
—45
90
135
180
—
ppm/V
Control Voltage Linearity4
LVC
BSL
–5
±1
+5
%
Incremental
–10
±5
+10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500
—
k
Nominal Control Voltage
VCNOM
@ fO
—3/8 x VDD
—V
Control Voltage Tuning Range
VC
0VDD
V
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 7.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±28% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 550CC50M0000BGR | VCXO, CLOCK, 50 MHz, CMOS OUTPUT |
| 550AB625M000BGR | VCXO, CLOCK, 625 MHz, LVPECL OUTPUT |
| 550AD707M300BGR | VCXO, CLOCK, 707.3 MHz, LVPECL OUTPUT |
| 550AE19M4400BGR | VCXO, CLOCK, 19.44 MHz, LVPECL OUTPUT |
| 550AC330M000BGR | VCXO, CLOCK, 330 MHz, LVPECL OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 550AE448M000DG | 制造商:Silicon Laboratories Inc 功能描述: |
| 550AE460M000DG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
| 550AE460M000DGR | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel |
| 550AE460M800DG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
| 550AE460M800DGR | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。