參數(shù)資料
型號(hào)： 552AE000274BGR
廠商： SILICON LABORATORIES
元件分類： VCXO, clock
英文描述： VCXO, CLOCK, 400 MHz, LVPECL OUTPUT
封裝： ROHS COMPLIANT, SMD, 6 PIN
文件頁數(shù)： 12/80頁
文件大?。?/td> 3734K
代理商： 552AE000274BGR
Si552
2
Rev. 0.5
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Voltage1
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
Supply Current
IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
120
108
99
90
130
117
108
98
mA
TriState mode
—
60
70
Frequency Select (FS)2
VIH
0.75 x VDD
——
V
VIL
——
0.5
Operating Temperature Range3
TA
–40
—
85
C
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. FS pin includes a 17 k
pullup resistor to VDD.
3. If the device is powered up below –20 C and the ambient temperature rises by approximately 105 C during normal
operation, the device will perform a one-time recalibration. The output is squelched for approximately 2–3 ms during
this recalibration.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope1,2,3
KV
10 to 90% of VDD
—45
90
135
180
—
ppm/V
Control Voltage Linearity4
LVC
BSL
–5
±1
+5
%
Incremental
–10
±5
+10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500
—
k
Nominal Control Voltage
VCNOM
@ fO
—3/8 x VDD
—V
Control Voltage Tuning Range
VC
0VDD
V
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 7.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±28% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
相關(guān)PDF資料
PDF描述
550AB000142BG VCXO, CLOCK, 188.859877 MHz, LVPECL OUTPUT
552AC000124BG VCXO, CLOCK, 212.5 MHz, LVPECL OUTPUT
554BF000196BGR VCXO, CLOCK, 666.51428 MHz, LVDS OUTPUT
552AD000253BGR VCXO, CLOCK, 176.83816 MHz, LVPECL OUTPUT
552AE000123BG VCXO, CLOCK, 166.62857 MHz, LVPECL OUTPUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
552AE000299DG 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 669.3265MHZ/670.8386MHZ VCXO LVPECL 6PIN - Trays
552AE000299DGR 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 669.3265MHZ/670.8386MHZ VCXO LVPECL 6PIN - Tape and Reel
552AE000394DG 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays
552AE000394DGR 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel
552AE000403DG 功能描述:644.53125MHz, 698.81233MHz LVPECL VCXO Pin Configurable Oscillator 6-SMD, No Lead (DFN, LCC) 3.3V 130mA Enable/Disable 制造商:silicon labs 系列:Si552 包裝:托盤 零件狀態(tài):有效 類型:VCXO 頻率 - 輸出 1:644.53125MHz，698.81233MHz 頻率 - 輸出 2:- 功能:啟用/禁用 輸出:LVPECL 電壓 - 電源:3.3V 頻率穩(wěn)定度:±20ppm 工作溫度:-40°C ~ 85°C 電流 - 電源（最大值）:130mA 大小/尺寸:0.276" 長(zhǎng) x 0.197" 寬（7.00mm x 5.00mm） 高度:0.071"（1.80mm） 封裝/外殼:6-SMD，無引線（DFN，LCC） 電流 - 電源（禁用）（最大值）:75mA 標(biāo)準(zhǔn)包裝:25
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*