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參數(shù)資料
| 型號(hào)： | 557GI05ALF |
| 英文描述： | Quad Differential PCI-Express Clock Source |
| 中文描述： | 四路差分個(gè)PCI - Express時(shí)鐘源 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 207K |
| 代理商： | 557GI05ALF |
Quad Differential PCI-Express Clock Source
MDS 557-05A E
4
Revision 011606
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS557-05A
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-05A must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01μF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Each 0.01μF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS557-05A.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
External Components
A minimum number of external components are
required for proper operation. Decoupling capacitors of
0.01
μ
F should be connected between VDD and GND
pairs (1,9 and 15,16) as close to the device as possible.
On chip capacitors
- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C
L
-12)*2 in this equation,
C
L
=crystal load capacitance in pf. For example, for a
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50
, then Rr =
475
(1%), providing IREF of 2.32 mA, output current
(I
OH
) is equal to 6*IREF.
Load Resistors R
L
Since the clock outputs are open source outputs, 50
ohm external resistors to ground are to be connected at
each clock output.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-05A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-05A can also be configured for LVDS
compatible voltage levels. See the
LVDS Compatible
Layout Guidelines
section.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 557GI-05ALF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 PCI-EXPRESS CLOCK SOURCE RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 557GI-05ALFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 PCI-EXPRESS CLOCK SOURCE RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 557GI06LF | 制造商:Integrated Device Technology Inc 功能描述: |
| 557GI-06LF | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PCI-EXPRESS CLOCK MUX (2:4) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 557GI-06LFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 PCI-EXPRESS CLOCK MUX (2:4) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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