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參數(shù)資料
| 型號： | 571DJAFREQDG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-8 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 315K |
| 代理商： | 571DJAFREQDG |
Si570/Si571
6
Rev. 0.31
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Programmable Frequency
Range1,2,3
fO
LVPECL/LVDS/CML
10
—
945
MHz
CMOS
10
—
160
Temperature Stability1,4
TA = –40 to +85 C
–20
–50
–100
—
+20
+50
+100
ppm
Aging
fa
Frequency drift over first year
—
±3
ppm
Frequency drift over 15 year life
—
±10
ppm
Total Stability
Temp stability = ±20 ppm
—
±31.5
ppm
Temp stability = ±50 ppm
—
±61.5
ppm
Absolute Pull Range1,4
APR
±25
—
±375
ppm
Power up Time5
tOSC
——
10
ms
Settling Time after Frequency
Change
tFRQ
f1 within ±100 ppm of f0
—
100
s
f1 > ±100 ppm of f0
——
10
ms
Notes:
1. See Section "7. Ordering Information" on page 21 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM =1/2 xVDD.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO.
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