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參數(shù)資料
| 型號： | 571QFAFREQDG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-8 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 315K |
| 代理商： | 571QFAFREQDG |
Si570/Si571
Rev. 0.31
17
Reset settings = 00xx xx00
Register 12. Reference Frequency
Bit
D7D6D5D4D3D2D1D0
Name
RFREQ[7:0]
Type
R/W
Bit
Name
Function
7:0
RFREQ[7:0]
Reference Frequency.
Frequency control input to DCO.
Register 135. Reset/Memory Control
Bit
D7D6D5D4D3D2D1D0
Name RST_REG
NewFreq
N/A
RECALL
Type
R/W
Bit
Name
Function
7
RST_REG
Internal Reset.
0 = Normal operation.
1 = Reset of all internal logic. Output tristated during reset.
Upon completion of internal logic reset, RST_REG is internally reset to zero.
6
NewFreq
New frequency applied.
Alerts the DSPLL that a new frequency configuration has been applied. This bit will
clear itself when the new frequency is applied.
5:1
N/A
Always zero.
0RECALL
Recall NVM into RAM.
0 = No operation.
1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
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