參數(shù)資料
型號: 5962-8780201RA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: QUAD, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP20
封裝: CERAMIC, DIP-20
文件頁數(shù): 5/16頁
文件大小: 307K
代理商: 5962-8780201RA
MAX4717/MAX4718
4.5
/20, 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
______________________________________________________________________________________
13
VGEN
GND
COM_
CL
VOUT
V+
VOUT
IN
OFF
ON
OFF
VOUT
Q = (
VOUT)(CL)
NC_
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
OFF
ON
OFF
IN
VIL TO VIH
V+
RGEN
IN_
MAX4717/
MAX4718
OR NO_
Figure 4. Charge Injection
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
+5V
VOUT
V+
IN_
NC1
COM1
NO1*
VIN
MAX4717/
MAX4718
OFF-ISOLATION = 20log
VOUT
VIN
ON-LOSS = 20log
VOUT
VIN
CROSSTALK = 20log
VOUT
VIN
NETWORK
ANALYZER
50
50
50
50
MEAS
REF
10nF
0V OR V+
50
GND
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
Figure 5. On-Loss, Off-Isolation, and Crosstalk
CAPACITANCE
METER
NC_ or
NO_
COM_
GND
IN
VIL OR VIH
10nF
V+
f = 1MHz
V+
MAX4717/
MAX4718
Figure 6. Channel Off/On-Capacitance
Test Circuits/Timing Diagrams (continued)
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