TL7702B, TL7705B
SUPPLY-VOLTAGE SUPERVISORS
SLVS037H – SEPTEMBER 1989 – REVISED JULY 1999
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
VS
10 k
0.1
F
SENSE
RESIN
GND
REF
RESET
VCC
CT
To System
RESET
RT
CT
System Supply
Reset Input
(from system)
To System
RESET
(see text)
7
2
1
3
5
6
8
4
10 k
Figure 8. System Reset Controller With Undervoltage Sensing
When the TL770xB SENSE terminal is used to monitor VCC, a current-limiting resistor in series with CT is
recommended. During normal operation, the timing capacitor is charged by the onboard current source to
approximately VCC or an internal voltage clamp (≈7.1-V zener), whichever is less. When the circuit is then subjected
to an undervoltage condition during which VCC is rapidly slewed down, the voltage on CT exceeds that on VCC. This
forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when VCC drops
below V(CT), not when VSENSE falls below VT–.
Texas Instruments performs a 100% electrical screen to verify that the outputs do not switch with 1 mA forced into
the CT terminal. Adding the external resistor, RT, prevents false triggering. Its value is calculated as follows:
V
(CT) * VT
*
R
T
Where:
V(CT) = VCC or 7.1 V, whichever is less
VT–
= 4.55 V (nom)
RT
= value of series resistor required
For VCC = 5 V:
5
* 4.55
R
T
t 1mA
Therefore,
R
T
u 450 W
Using a 20% tolerance resistor, RT should be greater than 560 .
Adding this series resistor changes the duration of the reset pulse by no more than 10%. RT extends the discharge
of CT, but also skews the V(CT) threshold. These effects tend to cancel one another. The precise percentage change
can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration
of the supply-voltage fault condition.
Both outputs of the TL770xB should be terminated with similar value resistors, even when only one is being used.
This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an
undefined state or delay system reset.