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參數(shù)資料
| 型號： | 5962-8876401LX |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, SKINNY, GLASS SEALED, CERDIP-24 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 361K |
| 代理商： | 5962-8876401LX |
AD7824/AD7828
REV. D
–9–
MODE 0
Figure 14 shows the timing diagram for Mode 0 operation. This
mode can only be used for microprocessors which have a WAIT
state facility, whereby a READ instruction cycle can be extended to
accommodate slow memory devices. A READ operation brings
CS and RD low which starts a conversion. The analog multiplexer
address inputs must remain valid while
CS and RD are low.
The data bus (DB7–DB0) remains in the three-state condition
until conversion is complete. There are two converter status
outputs on the AD7824/AD7828, interrupt (
INT) and ready
(RDY) which can be used to drive the microprocessor READY/
WAIT input. The RDY is an open drain output (no internal
pull-up device) which goes low on the falling edge of
CS and
goes high impedance at the end of conversion, when the 8-bit
conversion result appears on the data outputs. If the RDY status
is not required, then the external pull-up resistor can be omitted
and the RDY output tied to GND. The
INT goes low when
conversion is complete and returns high on the rising edge of
CS or RD.
MODE 1
Mode 1 operation is designed for applications where the micro-
processor is not forced into a WAIT state. A READ operation
takes
CS and RD low which triggers a conversion (see Figure
15). The multiplexer address inputs are latched on the rising
edge of
RD. Data from the previous conversion is read from the
three-state data outputs (DB7–DB0). This data may be disre-
garded if not required. Note, the RDY output (open drain out-
put) does not provide any status information in this mode and
must be connected to GND. At the end of conversion
INT
goes low. A second READ operation is required to access the
new conversion result. This READ operation latches a new
address into the multiplexer inputs and starts another conversion.
INT returns high at the end of the second READ operation,
when
CS or RD returns high. A delay of 2.5
s must be allowed
between READ operations.
Figure 14. Mode 0 Timing Diagram
Figure 15. Mode 1 Timing Diagram
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| 5962-8876402LX | 4-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP24 |
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| 5962-8876403XX | 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 |
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參數(shù)描述 |
|---|---|
| 5962-8876402LA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| 5962-8876402LX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC High Spd 4-CH 8-Bit CMOS IC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| 5962-8876403XA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| 5962-8876403XX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC High Spd 4-CH 8-Bit CMOS IC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| 5962-88764043A | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC High Spd 4-CH 8-Bit CMOS IC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
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