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參數(shù)資料
| 型號： | 5962-89621012A |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | OP-AMP, 10000 uV OFFSET-MAX, 40 MHz BAND WIDTH, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 365K |
| 代理商： | 5962-89621012A |
MICROCIRCUIT DATA SHEET
MNLM6161-X REV 2B1
(Absolute Maximum Ratings)
(Note 1)
Supply Voltage
36V
(V+ - V-)
Differential Input Voltage Range
(Note 4)
+8V
Common-Mode Voltage Range
(Note 6)
(V+ - 0.7V) to (V- - 7V)
Output Short Circuit to Gnd
(Note 3)
Continuous
Power Dissipation
(Note 2)
400mW
Soldering Information
260 C
(Soldering, 10 seconds)
Storage Temperature Range
-65 C to +150 C
Maximum Junction Temperature
150 C
Thermal Resistance
ThetaJA
90 C/W
LCC
(Still Air)
61 C/W
(500LF/Min Air flow)
113 C/W
CERDIP
(Still Air)
51 C/W
(500LF/Min Air flow)
228 C/W
CERPAK
(Still Air)
140 C/W
(500LF/Min Air flow)
228 C/W
CERAMIC SOIC
(Still Air)
140 C/W
(500LF/Min Air flow)
ThetaJC
20 C/W
LCC
21 C/W
CERDIP
21 C/W
CERPAK
21 C/W
CERAMIC SOIC
ESD Tolerance
(Note 4, 5)
+500V
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Operating Ratings indicate conditions for which the device is functional, but do not
guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade
when the device is not operated under the listed test conditions.
Note 2:
The maximum power dissipation must be derated at elevated temperatures and is
dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to
ambient thermal resistance), and TA (ambient temperature). The maximum allowable
power dissipation at any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the number
given in the Absolute Maximum Ratings, whichever is lower.
Note 3:
Continuous short-circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150 C.
Note 4:
In order to achieve optimum AC performance, the input stage was designed without
protective clamps. Exceeding the maximum differential input voltage results in
reverse breakdown of the base-emitter junction of one of the input transistors and
probable degradation of the input parameters (especially Vio, Iio and Noise).
Note 5:
The average voltage that the weakest pin combinations (those involving Pin 2 or Pin
3) can withstand and still conform to the datasheet limits. The test circuit used
consists of the human body model of 100pF in series with 1500 Ohms.
Note 6:
The voltage between V+ and either input pin must not exceed 36V.
3
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