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參數(shù)資料
| 型號(hào)： | 5962-8965701LX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大?。?/td> | 411K |
| 代理商： | 5962-8965701LX |
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MAX5487/MAX5488/MAX5489
Dual, 256-Tap, Nonvolatile, SPI-Interface,
Linear-Taper Digital Potentiometers
8
_______________________________________________________________________________________
Detailed Description
The MAX5487/MAX5488/MAX5489 contain two resistor
arrays, with 255 resistive elements each. The MAX5487
has an end-to-end resistance of 10k
, while the
MAX5488 and MAX5489 have resistances of 50k
and
100k
, respectively. The MAX5487/MAX5488/MAX5489
allow access to the high, low, and wiper terminals on
both potentiometers for a standard voltage-divider con-
figuration. Connect the wiper to the high terminal, and
connect the low terminal to ground, to make the device
a variable resistor (see Figure 1).
A simple 3-wire serial interface programs either wiper
directly to any of the 256 tap points. The nonvolatile
memory stores the wiper position prior to power-down
and recalls the wiper to the same point upon power-up
or by using an interface command (see Table 1). The
nonvolatile memory is guaranteed for 200,000 wiper
store cycles and 50 years for wiper data retention.
SPI Digital Interface
The MAX5487/MAX5488/MAX5489 use a 3-wire SPI-
compatible serial data interface (Figures 2 and 3). This
write-only interface contains three inputs: chip-select
(
CS), data clock (SCLK), and data in (DIN). Drive CS low
to enable the serial interface and clock data synchro-
nously into the shift register on each SCLK rising edge.
The WRITE commands (C1, C0 = 00 or 01) require 16
clock cycles to clock in the command, address, and data
(Figure 3a). The COPY commands (C1, C0 = 10, 11) can
use either eight clock cycles to transfer only command
and address bits (Figure 3b) or 16 clock cycles, with the
device disregarding 8 data bits (Figure 3a).
After loading data into the shift register, drive
CS high
to latch the data into the appropriate potentiometer
control register and disable the serial interface. Keep
CS low during the entire serial data stream to avoid cor-
ruption of the data.
Digital-Interface Format
The data format consists of three elements: command
bits, address bits, and data bits (see Table 1 and
Figure 3). The command bits (C1 and C0) indicate the
action to be taken such as changing or storing the
wiper position. The address bits (A1 and A0) specify
which potentiometer the command affects and the 8
data bits (D7 to D0) specify the wiper position.
PIN
TQFN
TSSOP
NAME
FUNCTION
114
VDD
Power Supply. Bypass VDD to GND with a 0.1F capacitor as close to the device as possible.
2
13
SCLK
Serial-Interface Clock Input
3
12
DIN
Serial-Interface Data Input
411
CS
Active-Low Chip-Select Digital Input
5, 6, 9
7, 9, 10
N.C.
No Connection. Not internally connected.
7
8
GND
Ground
8, 16
—
I.C.
Internally connected to EP. Leave unconnected.
10
6
LB
Low Terminal of Resistor B. The voltage at L can be greater than or less than the voltage at H.
Current can flow into or out of L.
11
5
WB
Wiper Terminal of Resistor B
12
4
HB
High Terminal of Resistor B. The voltage at H can be greater than or less than the voltage at L.
Current can flow into or out of H.
13
3
LA
Low Terminal of Resistor A. The voltage at L can be greater than or less than the voltage at H.
Current can flow into or out of L.
14
2
WA
Wiper Terminal of Resistor A
15
1
HA
High Terminal of Resistor A. The voltage at H can be greater than or less than the voltage at L.
Current can flow into or out of H.
—
EP
Exposed Pad (TQFN only). Internally connected to pins 8 and 16. Leave unconnected.
Pin Description
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| 5962-89657023A | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC DUAL 12 BIT RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時(shí)間: 最大工作溫度:+ 105 C 安裝風(fēng)格: 封裝 / 箱體:TSSOP 封裝:Reel |
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