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參數(shù)資料
| 型號： | 5962-8967401XX |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數(shù)： | 14/50頁 |
| 文件大?。?/td> | 520K |
| 代理商： | 5962-8967401XX |
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obtain the specified accuracy. Figure 11 illustrates
this operation. During pre-charge the charge on
the capacitor array first settles to the buffered
version of the analog input. This voltage is offset
from the actual input voltage. During fine-charge,
the charge then settles to the accurate unbuffered
version.
The acquisition time of the CS5012A/14/16 de-
pends on the CLKIN frequency. This is due to a
fixed pre-charge period. For instance, operating
the CS5012A -12, CS5014 -14 or CS5016 -16
version with an external 4 MHz CLKIN results in
a 3.75
s acquisition time: 1.5 s for pre-charging
(6 clock cycles) and 2.25
s for fine-charging.
Fine-charge settling is specified as a maximum of
2.25
s for an analog source impedance of less
than 200
. (For the CS5012A -7 version it is
specified as 1.32
s.) In addition, the comparator
requires a source impedance of less than 400
around 2 MHz for stability, which is met by prac-
tically all bipolar op amps. Large dc source
impedances can be accommodated by adding ca-
pacitance from AIN to ground (typically 200 pF)
to decrease source impedance at high frequencies.
However, high dc source resistances will increase
the input’s RC time constant and extend the nec-
essary acquisition time. For more information on
input applications, consult the application note:
Input Buffer Amplifiers for the CS501X Family of
A/D Converters.
During the first six clock cycles following a con-
version (pre-charge) in unipolar mode, the
CS5012A is capable of slewing at 20V/
s and the
CS5014/16 can slew at 5V/
s. In bipolar mode,
only half the capacitor array is connected to the
analog input so the CS5012A can slew at 40V/
s,
and the CS5014/16 can slew at 10V/
s. After the
first six CLKIN cycles, the CS5012A will slew at
1.25V/
s in unipolar mode and 3.0V/s in bipolar
mode, and the CS5014/16 will slew at 0.25V/
s
in unipolar mode and 0.5V/
s in bipolar mode.
Acquisition of fast slewing signals (step func-
tions) can be hastened if the step occurs during or
immediately following the conversion cycle. For
instance, channel selection in multiplexed appli-
cations should occur while the CS5012A/14/16 is
converting (see Figure 12). Multiplexer settling is
thereby removed from the overall throughput
equation, and the CS5012A/14/16 can convert at
full speed.
Convert Channel N+1
Convert Channel N
Address N
Address N + 1
Address N + 2
Address N + 3
EOC
Output
HOLD
Input
MUX
Address
MUX Settling
to Channel N + 2
Analog
Input
MUX Settling
to Channel N + 1
CS5012A/14/16
Figure 12. Pipelined MUX Input Channels
CS5012A, CS5014, CS5016
DS14F6
21
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