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參數(shù)資料
| 型號： | 5962-8967601QX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大?。?/td> | 3865K |
| 代理商： | 5962-8967601QX |
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7
Maxim Integrated
MAX5713/MAX5714/MAX5715
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
Note 3: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25°C.
Note 4: DC Performance is tested without load.
Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 6: Offset and gain errors are calculated from measurements made with VREF = VDD at code 30 and 4065 for MAX5715,
code 8 and 1016 for MAX5714, and code 2 and 254 for MAX5713.
Note 7: Subject to zero and full-scale error limits and VREF settings.
Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 9: On power-up, the device initiates an internal 200s (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 10: Guaranteed by design.
Note 11: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO.
Note 12: Daisy-chain speed is relaxed to accommodate (tCRF + tCSS0) with margin (derived specification, not production tested).
Note 13: This specification and its propagation through the chain limits how quickly an aborted daisy-chain command can be fol-
lowed by another daisy-chain command, to be applied on a per-device basis.
Figure 1. SPI Serial Interface Timing Diagram
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Fall to RDY Fall
tCRF
A
pplies to 24th SCLK falling edge,
CLOAD = 20pF
40
ns
SCLK Fall to RDY Hold
tCRH
A
pplies to 24th SCLK falling edge,
CLOAD = 0pF
2
ns
CSB Rise to RDY Rise
tCSR
CLOAD = 20pF (Note 13)
40
ns
DIN23
DIN22
DIN21
DIN20
DIN19
DIN18
DIN17
DIN16
DIN2
DIN1
tCSA
tCSF
tLDPW
tLDH
tCSH1
DIN0
DIN23
1
SCLK
CSB
DIN
23
45
67
82223241
tCSH0
tCSPW
tCLPW
tCSC
tCSS0
tCH
tCL
tDH
tDS
tSCLK
LDAC
CLR
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