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參數(shù)資料
| 型號： | 5962-9089401MEA |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 測量放大器 |
| 英文描述： | INSTRUMENTATION AMPLIFIER, 500 uV OFFSET-MAX, 4 MHz BAND WIDTH, CDIP16 |
| 封裝： | HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-16 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 464K |
| 代理商： | 5962-9089401MEA |
AD526
REV. D
–11–
OFFSET NULLING
Input voltage offset nulling of the AD526 is best accomplished
at a gain of 16, since the referred-to-input (RTI) offset is ampli-
fied the most at this gain and therefore is most easily trimmed.
The resulting trimmed value of RTI voltage offset typically
varies less than 3
V across all gain ranges.
Note that the low input current of the AD526 minimizes RTI
voltage offsets due to source resistance.
OUT
FORCE
OUT
SENSE
VOUT
0.1 F
–VS
0.1 F
+VS
VIN
16
15
14
13
12
11
10
9
12
34
56
78
+
–
AD526
16
84
21
GAIN NETWORK
A1
A0
CS CLK
A2
B
LOGIC AND LATCHES
20k
Figure 39. Offset Voltage Null Circuit
OUTPUT CURRENT BOOSTER
The AD526 is rated for a full
±10 V output voltage swing into
2 k
. In some applications, the need exists to drive more cur-
rent into heavier loads. As shown in Figure 40, a high current
booster may be connected “inside the loop” of the SPGA to
provide the required current boost without significantly degrad-
ing overall performance. Nonlinearities, offset and gain inaccu-
racies of the buffer are minimized by the loop gain of the
AD526 output amplifier.
OUT
FORCE
OUT
SENSE
–VS
0.1 F
+VS
VIN
16
15
14
13
12
11
10
9
12
34
56
78
+
–
AD526
16
84
21
GAIN NETWORK
A1
A0
CS CLK
A2
B
LOGIC AND LATCHES
HOS-100
0.01 F
0.1 F
0.01 F
RL
Figure 40. Current Output Boosting
CASCADED OPERATION
A cascade of two AD526s can be used to achieve binarily
weighted gains from 1 to 256. If gains from 1 to 128 are needed,
no additional components are required. This is accomplished by
using the B pin as shown in Figure 38. When the B pin is low,
the AD526 is held in a unity gain stage independent of the other
gain code values.
OFFSET NULLING WITH A D/A CONVERTER
Figure 41 shows the AD526 with offset nulling accomplished
with an 8-bit D/A converter (AD7524) circuit instead of the
potentiometer shown in Figure 39. The calibration procedure is
the same as before except that instead of adjusting the potenti-
ometer, the D/A converter corrects for the offset error. This
calibration circuit has a number of benefits in addition to elimi-
nating the trimpot. The most significant benefit is that calibra-
tion can be under the control of a microprocessor and therefore
can be implemented as part of an autocalibration scheme. Sec-
ondly, dip switches or RAM can be used to hold the 8-bit word
after its value has been determined. In Figure 42 the offset null
sensitivity, at a gain of 16, is 80
V per LSB of adjustment,
which guarantees dc accuracy to the 16-bit performance level.
OUT
FORCE
OUT
SENSE
VOUT
0.1 F
–VS
0.1 F
+VS
VIN
16
15
14
13
12
11
10
9
1
2
34
56
7
8
+
–
AD526
16
84
21
GAIN NETWORK
A1
A0
CS CLK
A2
B
LOGIC AND LATCHES
AD581 OR
AD587
+10V
VREF
7.5M
3.3M
AD548
0.01 F
–
+
+VS
–VS
ALL BYPASS CAPACITORS ARE 0.1 F
AD7524
GND
10 F
1k
OUT 1
OUT 2
+VS
MSB
LSB
CS
WR
Figure 41. Offset Nulling Using a DAC
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