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參數(shù)資料
| 型號： | 5962-9169001M3X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CQCC28 |
| 封裝： | CERAMIC, CC-28 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 294K |
| 代理商： | 5962-9169001M3X |
STANDARDIZED
MICROCIRCUIT DRAWING
DEFENSE ELECTRONICS SUPPLY CENTER
DAYTON, OHIO 45444
SIZE
A
5962-91690
REVISION LEVEL
B
SHEET
9
DESC FORM 193A
JUL 94
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/
-55°C
T +125°C
A
V
= +15 V, V
= +5 V,
CC
LOGIC
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
C
S
valid after CE
low
tHSR
See figure 6
9, 10, 11
All
0
ns
R/C
high after CE
low
tHRR
All
0
A valid after CE
0
low
tHAR
All
50
1/ 12/8
connected to V
, Ao and C
S
at logic "0", CE at logic "1". 10 V unipolar: 50
$
LOGIC
registor pin 8 to pin 10, 50
$ resistor pin 12 to ground. Analog input connected to pin 13.
20 V bipolar: 50
$ resistor pin 8 to pin 12, 50 resistor pin 8 to pin 10. Analog input
connected to pin 14. Unless otherwise noted, these conditions apply.
2/ Device types are tested to the conditions stated in table I, but are guaranteed to the specified
limits for the following variations in the supply voltage ranges. V
= +5 V to +5%,
LOGIC
V
= +12 V +5% and +15V to +10%, V
= -12 V +5% and -15 V +10%. (V
not required for
CC
EE
operation of devices 01, 02, and 04). For device type 03, V
= +5 V to ±10%.
LOGIC
3/ Maximum change in full scale calibration due to supply voltage shifts. Full scale calibration
to be measured at minimum and maximum voltage settings for each individual supply.
4/ +13.5 V < V
< +16.5 V, V
= 5 V, V
= -15 V and +11.4 V < V
< +12.6 V,
CC
LOGIC
EE
CC
V
= 5 V, V
= -12 V. (V
not required for operation of devices 01, 02 and 04).
LOGIC
EE
5/ 4.5 V < V
< 5.5 V, V
= 15V, V
= -15V. (V
not required for operation of devices 01, 02, and 04).
LOGIC
CC
EE
6/ -16.5 V < V
< -13.5 V, V
= 5 V, V
= +15 V and -12.6 V < V
< -11.4 V,
EE
LOGIC
CC
EE
V
= 5 V, V
= +12 V.
LOGIC
CC
7/ Reference should be buffered for operation on +12 V supplies. External load should not change
during conversion.
8/ For devices types 01, 02, and 04, 12/8
is not TTL compatible, must be hard-wired to V
or
LOGIC
digital common.
9/ Pulse width is measured at the Schottky TTL input logic threshold voltage (1.3 V).
10/ t
and t
are measured from the point when the input signal crosses the Schottky TTL
DS
DSC
logic threshold voltage (1.3 V) to when the STS output reaches 2.4 V. No external loading
is applied to STS.
11/ t
, t
, and t
are measured from the point when the input signal crosses the Schottky
HDR
HD
HL
TTL logic threshold voltage (1.3 V), to when the output voltage has moved 0.5 V in the direction
of its final high impedance output voltage. Each individual data bit (DBO - DB11) is measured
for both logic one to "high Z" and logic zero to "high Z" transitions. External loading is as
shown on figure 7.
12/ t
and t
are measured from the point when the input signal crosses the Schottky TTL
DDR
DD
logic threshold voltage (1.3 V), to when the output crosses either 2.4 V for a logic one, or
0.4 V for a logic zero. Each individual data bit (DBO - DB11) is measured for both "high Z" to
logic zero transitions. External loading is as shown on figure 8.
13/ t
is measured as the time from when the STS line crosses the 1.0 V level, going positive, to
C
when it crosses the 1.0 V level going negative. No external loading is applied to STS.
14/ Guaranteed by design.
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