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| 型號(hào)： | 5962-9169101M3A |
| 廠商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 封裝： | LCC-28 |
| 文件頁(yè)數(shù)： | 46/48頁(yè) |
| 文件大?。?/td> | 647K |
| 代理商： | 5962-9169101M3A |
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SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
VA+, VD+ = 5V
± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)
Parameter
Symbol
Min
Typ
Max
Units
CLKIN Period
(Note 18,24)
tclk
0.5
-
10
s
CLKIN Low Time
tclkl
200
-
ns
CLKIN High Time
tclkh
200
-
ns
Crystal Frequency
(Note 24, 25)
fxtal
0.9
1.6
2.0
MHz
SLEEP Rising to Oscillator Stable
(Note 26)
-
20
-
ms
RST Pulse Width
trst
150
-
ns
RST to STBY Falling
tdrrs
-
100
-
ns
RST Rising to STBY Rising
tcal
-
2,882,040
-
tclk
CH1/2 Edge to TRK1, TRK2 Rising
(Note 27)
tdrsh1
-80
-
ns
CH1/2 Edge to TRK1, TRK2 Falling
(Note 27)
tdfsh4
-
68tclk+260
ns
HOLD to SSH Falling
(Note 28)
tdfsh2
-60
ns
HOLD to TRK1, TRK2, Falling
(Note 28)
tdfsh1
66tclk
-
68tclk+260
ns
HOLD to TRK1, TRK2, SSH Rising
(Note 28)
tdrsh
-
120
-
ns
HOLD Pulse Width
(Note 29)
thold
1tclk+20
-
63tclk
ns
HOLD to CH1/2 Edge
(Note 28)
tdhlri
15
-
64tclk
ns
HOLD Falling to CLKIN Falling
(Note 29)
thcf
55
-
1tclk+10
ns
Note:
24. Minimum CLKIN period is 0.625
s in FRN mode (20 kHz sample rate). At temperatures >+85 °C,
and with clock frequencies <1.6 MHz, analog performance may be degraded.
25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency
is 1.6 MHz in FRN mode (20 kHz sample rate).
26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 M
parallel resistor (see Figure 8).
27. These times are for FRN mode.
28. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge
occurs after HOLD rises to 64 tclk after HOLD has fallen. These times are for PDT and RBT modes.
29. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must
be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN
after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as
narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after HOLD falls. This
ensures that the HOLD pulse will meet the minimum specification for thcf.
CS5102A
DS45F2
7
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