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參數(shù)資料
| 型號： | 5962-9175801MPX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | OP-AMP, 3500 uV OFFSET-MAX, 300 MHz BAND WIDTH, CDIP8 |
| 封裝： | CERDIP-8 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 359K |
| 代理商： | 5962-9175801MPX |
boosting amplifiers, such as the CLC420, you can't. For this
reason we provide data for both.
Slew rate is also different for inverting and non-inverting con-
figurations. This occurs because common-mode signal volt-
ages are present in non-inverting circuits but absent in
inverting circuits. Once again data is provided for both.
Transimpedance amplifier circuits
Low inverting, input current noise (2pA/
) makes the
CLC420 ideal for high sensitivity transimpedance amplifier
circuits for applications such as pin diode optical receivers,
and detectors in receiver IFs. However, feedback resistors
4k
or greater are required if feedback resistor noise current
is going to be less than the input current noise contribution of
the op amp.
With feedback resistors this large, shunt capacitance on the
inverting input of the op amp (from the pin diode, etc.) will
unacceptably degrade phase margin causing frequency re-
sponse peaking or oscillations a small valued capacitor shunt-
ing the feedback resistor solves this problem (Note: This
approach does not work for a current-feedback op amp con-
figured for transimpedance applications). To determine the
value of this capacitor, refer to the “Transimpedance BW vs.
R
f and Ci” plot.
For example, let's assume an optical transimpedance receiv-
er is being developed. Total capacitance from the inverting
input to ground, including the photodiode and strays is 5pF.
A 5k
feedback resistor value has been determined to pro-
vide best dynamic range based on the response of the pho-
todiode and the range of incident optical powers, etc. From
the “Transimpedance BW vs. R
f and Ci” plot, using Ci= 5pF it
is determined from the two curves labeled C
i = 5pF, that Cf =
1.5pF provides optimal compensation (no more than 0.5dB
frequency response peaking) and a 3dB bandwidth of ap-
proximately 27MHz.
Printed circuit layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. The amplifier is sensitive to stray
capacitance to ground at the output and inverting input: Node
connections should be small with minimal coupling to the
ground plane.
Parasitic or load capacitance directly on the output (pin 6) will
introduce additional phase shift in the loop degrading the loop
phase margin and leading to frequency response peaking. A
small series resistor before this capacitance, if present, ef-
fectively decouples this effect. The graphs on the preceding
page, “ Settling Time vs. C
L”, illustrates the required resistor
value and resulting performance vs. capacitance.
Evaluation PC boards (part no. 730013 for through-hole and
CLC730027 for SOIC) are available for the CLC420.
9
www.national.com
CLC420
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| 59629176402MXA | 制造商:AD 功能描述:* |
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