參數(shù)資料
型號(hào): 5962-9461116HTX
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: SRAM
英文描述: 512K X 32 MULTI DEVICE SRAM MODULE, 17 ns, CPGA66
封裝: PGA-66
文件頁(yè)數(shù): 8/12頁(yè)
文件大小: 223K
代理商: 5962-9461116HTX
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTE 5) (-55oC<T
A < 125
oC and -40oC to +85oC; V
CC = 5V +10%)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
READ cycle time
tRC
17
20
25
35
45
55
ns
Address access time
tAA
17
20
25
35
45
55
ns
Chip select access time
tACS
17
20
25
35
45
55
ns
Output hold from address change
tOH
22
2
ns
Chip select to output in Low-Z
tLZCS
2
ns
4,6,7
Chip select to output in High-Z
tHZCS
9
10
12
15
20
ns
4,6,7
Output enable access time
tAOE
910
12
15
20
ns
Output enable to output in Low-Z
tLZOE
0
ns
4,6
Output disable to output in High-Z
tHZOE
12
15
20
ns
4,6
WRITE cycle time
tWC
17
20
25
35
45
55
ns
Chip select to end of write
tCW
15
17
20
25
ns
Address valid to end of write
tAW
15
17
20
25
ns
Address setup time
tAS
22
2
ns
Address hold from end of write
tAH
11
1
ns
WRITE pulse width
tWP1
15
17
20
25
ns
WRITE pulse width
tWP2
15
17
20
25
ns
Data setup time
tDS
12
10
12
15
20
ns
Data hold time
tDH
00
0
ns
Write disable to output in Low-z
tLZWE
2
ns
4,6,7
Write enable to output in High-Z
tHZWE
9
11
13
15
ns
4,6,7
-45
-55
WRITE CYCLE
READ CYCLE
DESCRIPTION
-20
-17
-25
SYMBOL
NOTES
UNITS
-35
相關(guān)PDF資料
PDF描述
5962-9560011QUA 512K X 8 STANDARD SRAM, 25 ns, CDSO32
5962-9561320HTC 512K X 8 STANDARD SRAM, 45 ns, CDSO32
5962-9561328HTC 512K X 8 STANDARD SRAM, 12 ns, CDSO32
5962-9560013QZA 512K X 8 STANDARD SRAM, 15 ns, CDSO32
5962-9561328H9C 512K X 8 STANDARD SRAM, 12 ns, CDFP32
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