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參數(shù)資料
| 型號(hào)： | 5962-9853801Q2A |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 3/37頁 |
| 文件大?。?/td> | 693K |
| 代理商： | 5962-9853801Q2A |
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 5. Conversion Rate and Power Consumption Selection
CONVERSION TIME
AVAILABLE VCC
TYPICAL SUPPLY CURRENT, ICC
CONVERSION RATE
CONVERSION TIME,
tconv
AVAILABLE VCC
RANGE
INPUT DATA
OPERATING
POWER
DOWN
Fast conversion speed
7
s typ
5.5 V to 3.3 V
9h
0.6 mA typ
1.5 mA max
1
A typ
Slow conversion speed
15
s typ
5.5 V to 2.7 V
Ah
0.4 mA typ
1 mA max
1
A typ
programmable power-down state
The device is put into the power-down state by writing 8h to DATA IN. The power-up state is restored during
the next active access by pulling CS low. The conversion rate selected before the device is put into the
power-down state is not affected by the power-down mode. Power-down can be used to achieve even lower
power consumption. This is because the sustaining power (when not converting) is only 1.3 mA maximum and
standby power is only 1
A maximum. (By averaging out the power consumption can be much lower than the
1 mA peak when the conversion throughput is lower.)
Power Down
CS
EOC
ICC
DATA IN
Hi-Z
0
Supply Current
1
00 0
1 mA
(Typical Peak Supply)
0.3 mA
(Typical Sustaining)
0.0007 mA
(Typical Power Down
Supply)
Figure 3. Typical Supply Current During Conversion/Power Down
power up and initialization
After power up, if operating in DSP mode, CS and FS must be taken from high to low to begin an I/O cycle. EOC
is initially high, and the input data register is set to all zeroes. The content of the output data register is random,
and the first conversion result should be ignored. For initialization during operation, CS is taken high and
returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down
state can be invalid and should be disregarded.
When power is first applied to the device, the conversion rate must be programmed, and the internal Async Flag
must be taken low once. The rising edge of CS of the same cycle then takes Async Flag low.
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