參數(shù)資料
型號(hào)： 5962-9955701QPA
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, CDIP8
封裝： CERAMIC, DIP-8
文件頁(yè)數(shù)： 2/23頁(yè)
文件大?。?/td> 633K
代理商： 5962-9955701QPA
TLV5618A
2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230H – JULY 1999 – REVISED JULY 2002
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5618A is a dual 12-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial
interface, a speed and power down control logic, a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by the reference) is given by:
2REF
CODE
2n
[V]
Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n–1, where
n=12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 12 shows examples of how to connect the TLV5618A to TMS320, SPI, and Microwire.
TMS320
DSP FSX
CLKX
DX
TLV5618A
SCLK
DIN
CS
SPI
I/O
SCK
MOSI
TLV5618A
SCLK
DIN
CS
Microwire
I/O
SK
SO
TLV5618A
SCLK
DIN
CS
Figure 12. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be
performed to program the TLV5618A. After the write operation(s), the holding registers or the control register
are updated automatically on the next positive clock edge following the 16th falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax +
1
t
whmin )
t
wlmin
+ 20 MHz
The maximum update rate is:
f
updatemax +
1
16 t
whmin )
t
wlmin
+ 1.25 MHz
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5618A should also be considered.
相關(guān)PDF資料
PDF描述
TLV5618ACDR SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO8
TLV5618AID SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO8
TLV5618AMJG SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, CDIP8
TLV5618ACP SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDIP8
TLV5618AQDRG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO8
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