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參數(shù)資料
| 型號： | 5962-9955702Q2A |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 12-BIT DAC, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 480K |
| 代理商： | 5962-9955702Q2A |
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156G – JULY 1997 – REVISED APRIL 2001
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in, most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked
into the input register.
The 16 bits of data can be transferred with the sequence shown in Figure 18.
D15
D14
D13
D12
D11
12 Data Bits
D0
Program Bits
Data Bits
16 Bits
MSB (Input Word)
MSB (Data)
LSB (Data, Input Word)
Figure 18. Input Data Word Format
Table 2 shows the function of program bits D15 – D12.
Table 2. Program Bits D15 – D12 Function
PROGRAM BITS
DEVICE FUNCTION
D15
D14
D13
D12
DEVICE FUNCTION
1
X
Write to latch A with serial interface register data
and latch B updated with buffer latch data
0
X
0
Write to latch B and double buffer latch
0
X
1
Write to double buffer latch only
X
0
X
12.5
s settling time
X
1
X
2.5
s settling time
X
0
X
Powered-up operation
X
1
X
Power down mode
function of the latch control bits (D15 and D12)
Three data transfers are possible. All transfers occur immediately after CS goes high and are described in the
following sections.
latch A write, latch B update (D15 = high, D12 = X)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to
latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output
updates of both DACs.
Serial
Interface
Register
D12 = X
D15 = High
Latch A
Latch B
Double
Buffer Latch
To DAC A
To DAC B
Figure 19. Latch A Write, Latch B Update
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9955702QPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 5962-9956903QXC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 205MHz 0.35um (CMOS) Technology 3.3V/5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 205MHz 0.35um Technology 3.3V/5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM 3.3V/5V 256CQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM 3.3V/5V 256CQFP - Trays |
| 5962-9956903QYC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 205MHz 0.35um Technology 3.3V/5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays |
| 5962-9956904QXC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 240MHz 0.35um Technology 3.3V/5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM 3.3V/5V 256CQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM 3.3V/5V 256CQFP - Trays |
| 5962-9956904QYC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 240MHz 0.35um Technology 3.3V/5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays |
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