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| 型號： | 5962-9955702QPA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 12-BIT DAC, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 480K |
| 代理商： | 5962-9955702QPA |
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156G – JULY 1997 – REVISED APRIL 2001
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
latch B and double-buffer 1 write (D15 = low, D12 = low)
The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
Serial
Interface
Register
D12 = Low
D15 = Low
Latch A
Latch B
Double
Buffer Latch
To DAC A
To DAC B
Figure 20. Latch B and Double-Buffer Write
double-buffer-only write (D15 = low, D12 = high)
The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
Serial
Interface
Register
D12 = High
D15 = Low
Latch A
Latch B
Double
Buffer
To DAC A
To DAC B
Figure 21. Double-Buffer-Only Write
purpose and use of the double buffer
Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change
after a single write. This is achieved by the two following steps.
1.
A double-buffer-only write is executed to store the new DAC B data without changing the DAC A and B
outputs.
2.
Following the previous step, a write to latch A is executed. This writes the SIR data to latch A and also
writes the double-buffer contents to latch B. Thus both DACs receive their new data at the same time,
and so both DAC outputs begin to change at the same time.
Unless a double-buffer-only write is issued, the latch B and double-buffer contents are identical. Thus, following
a write to latch A or B with another write to latch A does not change the latch B contents.
operational examples
changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g., after power up), the latch can be filled with 1s by writing (bit D15
on the left, D0 on the right)
1X0X 1111 1111 1111
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The other X can be
zero or one (don’t care).
The latch B contents and the DAC B output are not changed by this write unless the double-buffer contents are
different from the latch B contents. This can only be true if the last write was a double-buffer-only write.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9956903QXC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 205MHz 0.35um (CMOS) Technology 3.3V/5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 205MHz 0.35um Technology 3.3V/5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM 3.3V/5V 256CQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM 3.3V/5V 256CQFP - Trays |
| 5962-9956903QYC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 205MHz 0.35um Technology 3.3V/5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 205MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays |
| 5962-9956904QXC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 240MHz 0.35um Technology 3.3V/5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM 3.3V/5V 256CQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM 3.3V/5V 256CQFP - Trays |
| 5962-9956904QYC | 制造商:Microsemi Corporation 功能描述:FPGA 16K Gates 924 Cells 240MHz 0.35um Technology 3.3V/5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA 16K GATES 924 CELLS 240MHZ 0.35UM (CMOS) TECHNOLOGY 3.3 - Trays |
| 5962-9957001Q2A | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
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