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參數(shù)資料
| 型號(hào)： | 5962-9959101QPA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 3-CHANNEL POWER SUPPLY SUPPORT CKT, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 248K |
| 代理商： | 5962-9959101QPA |
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TPS330718M
TRIPLE PROCESSOR SUPERVISORS
SGLS133A JANUARY 2003 REVISED DECEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the
following supply voltage monitoring table.
SUPPLY VOLTAGE MONITORING
DEVICE
NOMINAL SUPERVISED VOLTAGE
THRESHOLD VOLTAGE (TYP)
DEVICE
SENSE1
SENSE2
SENSE3
SENSE1
SENSE2
SENSE3
TPS3307-18
3.3 V
1.8 V
User defined
2.93 V
1.68 V
1.25 V
The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain
below the threshold voltage VIT+.
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset.
The delay time, td typ = 200 ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+. When
the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low)
again.
The TPS3307-18 incorporates a manual reset input, MR. A low level at MR causes RESET to become active.
In addition to the active-low RESET output, the TPS3307-18 includes an active-high RESET output.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
55
°C to 125°C
Ceramic Dual In Line (JG)
TPS3307-18MJGB
55
°C to 125°C
Leadless Ceramic Chip Carrier (FK)
TPS3307-18MFKB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION/TRUTH TABLES
MR
SENSE1>VIT1
SENSE2>VIT2
SENSE3>VIT3
RESET
L
X
L
H
0
L
H
0
1
L
H
0
1
0
L
H
0
1
L
H
1
0
L
H
1
0
1
L
H
1
0
L
H
1
H
L
X = Don’t care
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